Method and system for validating a hierarchical simulation database

• US 20070044051A1
• Filed: 08/17/2005
• Published: 02/22/2007
• Est. Priority Date: 08/17/2005
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Kong, Jun, McGaughy, Bruce
• Granted Patent: US 7,434,183 B2
• Time in Patent Office: Days
• US Class Current: 716/115
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

System and method for validating a circuit for simulation are disclosed. The system includes at least one processing unit for executing computer programs, a graphical user interface for viewing representations of the circuit on a display, a memory for storing information of the circuit, and logic for representing the circuit in a hierarchical data structure, where the hierarchical data structure has a plurality of subcircuits arranged in a connected graph, and where each subcircuit has circuit elements and one or more input and output ports. The system further includes logic for traversing the hierarchical data structure in a bottom-up fashion, logic for recording input port to output port (port-to-port) properties of the subcircuits in the hierarchical data structure, logic for traversing the hierarchical data structure in a top-down fashion, and logic for identifying illegal port paths using the port-to-port properties of the subcircuits.

Claims

1. A method for validating a circuit for simulation, comprising:

representing the circuit in a hierarchical data structure, wherein the hierarchical data structure comprises a plurality of subcircuits arranged in a connected graph, wherein each subcircuit comprises circuit elements and one or more input and output ports;

traversing the hierarchical data structure in a bottom-up fashion;

recording input port to output port (port-to-port) properties of the subcircuits in the hierarchical data structure;

traversing the hierarchical data structure in a top-down fashion; and

identifying illegal port paths using the port-to-port properties of the subcircuits.

2. The method of claim 1, wherein traversing the hierarchical data structure in a bottom-up fashion comprises:

traversing the hierarchical data structure in a breadth-first-search.

3. The method of claim 1, wherein traversing the hierarchical data structure in a bottom-up fashion comprises:

traversing the hierarchical data structure in a depth-first-search.

4. The method of claim 1, wherein recording port-to-port properties comprises:

determining potentially illegal paths within each subcircuit in accordance with a set of predetermined rules; and

marking each input port and output port as either a legal port or a potentially illegal port in accordance with the potentially illegal paths within each subcircuit.

5. The method of claim 1, wherein identifying illegal port paths comprises:

detecting voltage source(s) only paths; and

reporting the voltage source(s) only paths.

6. The method of claim 1, wherein identifying illegal port paths comprises:

detecting inductor(s) only paths; and

reporting the inductor(s) only paths.

7. The method of claim 1, wherein identifying illegal port paths comprises:

detecting voltage source(s) and/or inductor(s) paths; and

reporting the voltage source(s) and/or inductor(s) paths.

8. The method of claim 1, wherein identifying illegal port paths further comprises:

detecting illegal port paths using connectivity information of the subcircuits.

9. The method of claim 1 further comprises:

communicating port-to-port properties of the plurality of subcircuits in the hierarchical data structure;

grouping functional calls to the plurality of subcircuits according to commonality of port-to-port properties; and

simulating the plurality of subcircuits using the functional calls.

10. The method of claim 1 further comprises:

communicating port-to-port properties of the plurality of subcircuits in the hierarchical data structure;

splitting subcircuits if corresponding functional calls have different port-to-port properties; and

simulating the subcircuits using the functional calls.

11. A system for validating a circuit for simulation, comprising:

at least one processing unit for executing computer programs;

a graphical user interface for viewing representations of the circuit on a display;

a memory for storing information of the circuit;

logic for representing the circuit in a hierarchical data structure, wherein the hierarchical data structure comprises a plurality of subcircuits arranged in a connected graph, wherein each subcircuit comprises circuit elements and one or more input and output ports;

logic for traversing the hierarchical data structure in a bottom-up fashion;

logic for recording input port to output port (port-to-port) properties of the subcircuits in the hierarchical data structure;

logic for traversing the hierarchical data structure in a top-down fashion; and

logic for identifying illegal port paths using the port-to-port properties of the subcircuits.

12. The system of claim 11, wherein logic for traversing the hierarchical data structure in a bottom-up fashion comprises:

logic for traversing the hierarchical data structure in a breadth-first-search.

13. The system of claim 11, wherein logic for traversing the hierarchical data structure in a bottom-up fashion comprises:

logic for traversing the hierarchical data structure in a depth-first-search.

14. The system of claim 11, wherein logic for recording port-to-port properties comprises:

logic for determining potentially illegal paths within each subcircuit in accordance with a set of predetermined rules; and

logic for marking each input port and output port as either a legal port or a potentially illegal port in accordance with the potentially illegal paths within each subcircuit.

15. The system of claim 11, wherein logic for identifying illegal port paths comprises:

logic for detecting voltage source(s) only paths; and

logic for reporting the voltage source(s) only paths.

16. The system of claim 11, wherein logic for identifying illegal port paths comprises:

logic for detecting inductor(s) only paths; and

logic for reporting the inductor(s) only paths.

17. The system of claim 11, wherein logic for identifying illegal port paths comprises:

logic for detecting voltage source(s) and/or inductor(s) paths; and

logic for reporting the voltage source(s) and/or inductor(s) paths.

18. The system of claim 11, wherein logic for identifying illegal port paths further comprises:

logic for detecting illegal port paths using connectivity information of the subcircuits.

19. The system of claim 11 further comprises:

logic for communicating port-to-port properties of the plurality of subcircuits in the hierarchical data structure;

logic for grouping functional calls to the plurality of subcircuits according to commonality of port-to-port properties; and

logic for simulating the plurality of subcircuits using the functional calls.

20. The system of claim 11 further comprises:

logic for communicating port-to-port properties of the plurality of subcircuits in the hierarchical data structure;

logic for splitting subcircuits if corresponding functional calls have different port-to-port properties; and

logic for simulating the subcircuits using the functional calls.

21. A computer program product for validating a circuit for simulation, comprising a medium storing computer programs for execution by one or more computer systems having at least a processing unit, a user interface and a memory, the computer program product comprising:

code for representing the circuit in a hierarchical data structure, wherein the hierarchical data structure comprises a plurality of subcircuits arranged in a connected graph, wherein each subcircuit comprises circuit elements and one or more input and output ports;

code for traversing the hierarchical data structure in a bottom-up fashion;

code for recording input port to output port (port-to-port) properties of the subcircuits in the hierarchical data structure;

code for traversing the hierarchical data structure in a top-down fashion; and

code for identifying illegal port paths using the port-to-port properties of the subcircuits.

22. The computer program product of claim 21, wherein code for traversing the hierarchical data structure in a bottom-up fashion comprises:

code for traversing the hierarchical data structure in a breadth-first-search.

23. The computer program product of claim 21, wherein code for traversing the hierarchical data structure in a bottom-up fashion comprises:

code for traversing the hierarchical data structure in a depth-first-search.

24. The computer program product of claim 21, wherein code for recording port-to-port properties comprises:

code for determining potentially illegal paths within each subcircuit in accordance with a set of predetermined rules; and

code for marking each input port and output port as either a legal port or a potentially illegal port in accordance with the potentially illegal paths within each subcircuit.

25. The computer program product of claim 21, wherein code for identifying illegal port paths comprises:

code for detecting voltage source(s) only paths; and

code for reporting the voltage source(s) only paths.

26. The computer program product of claim 21, wherein code for identifying illegal port paths comprises:

code for detecting inductor(s) only paths; and

code for reporting the inductor(s) only paths.

27. The computer program product of claim 21, wherein code for identifying illegal port paths comprises:

code for detecting voltage source(s) and/or inductor(s) paths; and

code for reporting the voltage source(s) and/or inductor(s) paths.

28. The computer program product of claim 21, wherein code for identifying illegal port paths further comprises:

code for detecting illegal port paths using connectivity information of the subcircuits.

29. The computer program product of claim 21 further comprises:

code for communicating port-to-port properties of the plurality of subcircuits in the hierarchical data structure;

code for grouping functional calls to the plurality of subcircuits according to commonality of port-to-port properties; and

code for simulating the plurality of subcircuits using the functional calls.

30. The computer program product of claim 21 further comprises:

code for communicating port-to-port properties of the plurality of subcircuits in the hierarchical data structure;

code for splitting subcircuits if corresponding functional calls have different port-to-port properties; and

code for simulating the subcircuits using the functional calls.