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Method and system for validating a hierarchical simulation database

  • US 20070044051A1
  • Filed: 08/17/2005
  • Published: 02/22/2007
  • Est. Priority Date: 08/17/2005
  • Status: Active Grant
First Claim
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1. A method for validating a circuit for simulation, comprising:

  • representing the circuit in a hierarchical data structure, wherein the hierarchical data structure comprises a plurality of subcircuits arranged in a connected graph, wherein each subcircuit comprises circuit elements and one or more input and output ports;

    traversing the hierarchical data structure in a bottom-up fashion;

    recording input port to output port (port-to-port) properties of the subcircuits in the hierarchical data structure;

    traversing the hierarchical data structure in a top-down fashion; and

    identifying illegal port paths using the port-to-port properties of the subcircuits.

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