System and Technique of Pattern Matching and Pattern Replacement

• US 20070044060A1
• Filed: 01/25/2006
• Published: 02/22/2007
• Est. Priority Date: 08/16/2005
• Status: Active Grant

• Current Assignee: Pulsic Limited
• Original Assignee: Pulsic Limited
• Inventors: Waller, Mark
• Granted Patent: US 7,657,852 B2
• Time in Patent Office: Days
• US Class Current: 716/52
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A system and technique to specifies patterns to search for in an integrated circuit layout, and specifies proposed replacement patterns. A description file includes specifications for one or more patterns to be searched for. In the description file, for each pattern, there may be one or more proposed replacement patterns. The description file is read. Pattern matches, if any, in a layout are found. A proposed replacement pattern is tested in place of a matched pattern. If acceptable, the proposed pattern may be used to replace the matched pattern.

Claims

1. A method comprising:

reading a description file comprising a plurality of pattern definitions, each described using a sequence of tokens of a pattern description language;

storing the plurality of pattern definitions in a memory of a computer; and

using the computer, checking a layout feature against the plurality of pattern definitions to find any pattern matches.

2. The method of claim 1 wherein the pattern description language comprises:

a first token describing a track in a first direction;

a second token describing a track in a second direction;

a third token describing a track in a third direction; and

a fourth token describing a track in a fourth direction, wherein the first and second directions are orthogonal to the third and fourth directions.

3. The method of claim 1 wherein the pattern description language comprises:

a first token describing a track in a first or a second direction; and

a second token describing a track in a third or a fourth direction, wherein the first and second directions are orthogonal to the third and fourth directions.

4. The method of claim 1 wherein the pattern description language comprises a token describing a via.

5. The method of claim 1 wherein the pattern description language comprises a token describing T junction or termination point.

6. The method of claim 1 wherein the pattern description language comprises a wild card token describing matching any track.

7. The method of claim 1 wherein each pattern definition has a priority token, indicating a relative priority of a pattern to other patterns.

8. The method of claim 1 wherein the description file further comprises for each pattern definition, at least one pattern replacement proposal description.

9. The method of claim 1 wherein the storing the plurality of pattern definitions in a memory of a computer is replaced by compiling the description file into executable code, and the using the computer, checking a layout feature against the plurality of pattern definitions to find any pattern matches comprises running the executable code.

10. The method of claim 1 further comprising:

for a pattern match, replacing the layout feature with a first proposed replacement pattern associated with the pattern match;

performing a first check on the first proposed replacement pattern;

if the first check does not pass, replacing the first proposed replacement pattern with a second proposed replacement pattern associated with the pattern match; and

performing a second check on the second proposed replacement pattern.

29. The method of claim 1 wherein the pattern description language comprises:

a first token describing a track in a first or a second direction; and

a second token describing a track in the first or second directions.

30. The method of claim 10 further comprising:

if the second check does not pass, replacing the second proposed pattern with the layout feature.

11. A computer-readable medium storing a plurality of data structures, each data structure comprising:

a pattern definition section comprising a description of a pattern to be searched for in circuit layout database; and

a pattern proposal section comprising a description of at least one proposed replacement pattern for the pattern described in the pattern definition section.

12. The computer-readable medium of claim 11 wherein the patter proposal section comprises at least two proposed replacement patterns.

13. The computer-readable medium of claim 11 wherein each data structure further comprises:

a priority definition section, describing a relative priority of a data structure to other data structures on the computer-readable medium.

14. The computer-readable medium of claim 11 wherein the pattern definition section comprises a field to describe the pattern using a sequence of alphanumeric characters indicating a characteristic of the pattern to be searched for.

15. The computer-readable medium of claim 14 wherein one or more alphanumeric characters are used to designate a via, a track in a first direction, a track in a second direction, a track in a third direction, a track in a fourth direction, a track in the first or third direction, a track in the second or fourth direction, or a T junction or termination point.

16. A system comprising:

a storage device;

a memory; and

a processor, wherein the processor is programmed to

read a description file, stored on the storage device, comprising a plurality of pattern definitions, each described using a sequence of tokens of a pattern description language, load the plurality of pattern definitions into the memory, and

check a circuit layout feature against each of the pattern definitions to find any pattern matches.

17. The system of claim 16 wherein the storage device, memory, and processor are coupled to a network.

18. The system of claim 16 wherein the storage device, memory, and processor are coupled to a system bus.

19. The system of claim 16 wherein the processor is programmed to

edit the description file to add a new pattern definition to the plurality of pattern definitions, and

after adding the new pattern definition, check the circuit layout feature against each of the pattern definitions, including the new pattern definition, to find any pattern matches.

20. The system of claim 16 wherein the processor is programmed to

for a pattern match and the circuit layout feature is an interconnect track of width X,

replace circuit layout feature with a interconnect track of width Y, where Y is greater than X.

21. The system of claim 16 wherein the processor is programmed to

for a pattern match and the circuit layout feature is an interconnect track of width X,

replace circuit layout feature with a interconnect track of width Y, where Y is less than X.

22. The system of claim 16 wherein the processor is programmed to

for a pattern match, replacing the circuit layout feature with a proposed pattern provided in the description file.

31. The system of claim 16 wherein the processor is programmed to

for a pattern match, moving the circuit layout feature to a different position.

32. The system of claim 31 wherein the circuit layout feature comprises at least one of a via, contact, or interconnect track.

33. The system of claim 16 wherein the processor is programmed to

for a pattern match, replacing the circuit layout feature with a replacement circuit layout feature in a different position.

34. The system of claim 31 wherein the circuit layout feature comprises at least one of a via, contact, or interconnect track.

23. A graphical user interface having windowing capability comprising:

first windowing means for editing a description file comprising a plurality of pattern definitions, each described using a sequence of tokens of a pattern description language, and at least one pattern replacement proposal description; and

second windowing means for displaying results of a check of a layout feature against the plurality of pattern definitions to find any pattern matches.

24. The graphical user interface of claim 23 wherein the description file is an ASCII file.

25. A method comprising:

permitting editing of a description file to add a new pattern definition to a plurality of preexisting pattern definitions; and

providing a software program to read the description file, after a new pattern definition has been added,

wherein the software program checks a circuit layout feature against each of the preexisting pattern definitions and the new pattern definition to find any pattern matches.

26. The method of claim 25 wherein the description file is in ASCII format and may be edited by a user of the software program.

27. The method of claim 25 wherein when the description file is encrypted, decrypting the description before editing and before the software program loads the description file.

28. The method of claim 25 wherein the circuit layout feature is an automatically generated interconnect track.