Hardware key control of debug interface

• US 20070044158A1
• Filed: 11/04/2005
• Published: 02/22/2007
• Est. Priority Date: 04/20/2005
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Dalzell, William, Cruzado, Edwin, Bernier, Brian
• Granted Patent: US 7,509,250 B2
• Time in Patent Office: Days
• US Class Current: 726/27
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: H04L 9/065 Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3

Abstract

In one embodiment, a system comprises debug functionality, a debug interface communicatively coupled to the debug functionality, and a hardware key interface. Communication with the debug functionality over the debug interface is not permitted if an authorized hardware key is not communicatively coupled to the hardware key interface.

Claims

1. A system comprising:

debug functionality;

a debug interface communicatively coupled to the debug functionality;

a hardware key interface;

wherein communication with the debug functionality over the debug interface is not permitted if an authorized hardware key is not communicatively coupled to the hardware key interface.

2. The system of claim 1, further comprising a hardware key monitor, wherein the hardware key monitor determines when a hardware key is communicatively coupled to the hardware key interface and whether the hardware key is an authorized hardware key.

3. The system of claim 1, further comprising application-specific functionality, wherein the debug functionality interacts with at least a portion of the application-specific functionality.

4. The system of claim 3, wherein the application-specific functionality comprises the debug functionality.

5. The system of claim 1, wherein the hardware key interface comprises at least one of:

a connector for physically coupling the hardware key to the hardware key interface and a wireless interface for wirelessly communicatively coupling the authorized key to the hardware key interface.

6. The system of claim 1, wherein the debug interface comprises a JTAG interface.

7. The system of claim 1, wherein the hardware key interface comprises at least one of a universal serial bus interface and a RS-232 serial interface.

8. A system comprising:

debug functionality;

a debug interface communicatively coupled to the debug functionality;

a hardware key interface;

wherein communication with the debug functionality over the debug interface is not permitted unless key information is received from a hardware key communicatively to the hardware key interface.

9. The system of claim 8, wherein when data is received from the hardware key, the system determines if the received data comprises the key information.

10. The system of claim 9, wherein the key information comprises a key bit stream, wherein the system determines if the received data comprises the key bit stream.

11. The system of claim 8, wherein the hardware key interface comprises a clock line on which a clock signal output by a hardware key when the hardware key is communicatively coupled to the hardware key interface, wherein the clock signal is used to clock data communicated over the hardware key interface between the hardware key and the system.

12. The system of claim 11, further comprising a clock, wherein when the hardware key is communicatively coupled to the hardware key interface, the clock is used to synchronize, to the clock signal received on the clock line of the hardware key interface, at least a portion of processing performed by the system.

13. The system of claim 11, wherein the system generates the key bit stream for use in determining if the received data comprises the key bit stream.

14. The system of claim 13, wherein when the hardware key is communicatively coupled to the hardware key interface and a polynomial is received on the hardware key interface from the hardware key, the polynomial is used by the system to generate the key bit stream.

15. The system of claim 14, wherein the polynomial comprises a seed value and one or more attributes used to generate the key bit stream.

16. The system of claim 14, wherein the key bit stream is generated using a linear shift feedback register that outputs a stream cipher, wherein the polynomial comprises a seed value, a length of the linear shift feedback register, and one or more taps of the linear shift feedback register.

17. A method comprising:

determining when a debug device external to a system is attempting to communicate over a debug interface of the system; and

when the debug device external to the system is attempting to communicative over the debug interface;

determining if an authorized hardware key is communicatively coupled to the system; and

preventing communications from occurring over the debug interface between the debug device and the system if an authorized hardware key is not communicatively coupled to the system.

18. The method of claim 17, wherein when the debug device external to the system is attempting to communicative over the debug interface, permitting communications over the debug interface between the debug device and the system if an authorized hardware key is communicatively coupled to the system.

19. The method of claim 17, wherein when the debug device external to the system is attempting to communicative over the debug interface, considering an intrusion attempt to have occurred if an authorized hardware key is not communicatively coupled to the system.

20. The method of claim 17, wherein determining if an authorized hardware key is communicatively coupled to the system comprises at least one of determining if an authorized hardware key is physically coupled to a connector of the system and determining if an authorized key is wirelessly coupled to a wireless interface of the system.

21. A system comprising:

application-specific functionality comprising debug functionality;

a debug interface to communicatively couple a debug device to the system in order to communicate with the debug functionality;

wherein the debug device is not permitted to communicate with the debug functionality unless an authorized hardware key is communicatively coupled to the system.

22. The system of claim 21, further comprising a hardware key monitor to determine when the authorized hardware key is communicatively coupled to the system.

23. The system of claim 21, further comprising a hardware key interface to communicatively couple the authorized hardware key to the system.

24. Apparatus comprising:

a hardware key interface to communicatively couple a hardware key to the apparatus; and

a hardware key monitor to determine when the hardware key is communicatively coupled to the apparatus and to determine if the hardware key is authorized;

an output that indicates that when communications should not be permitted over a debug interface;

wherein the output indicates that communication should not be permitted over the debug interface if a hardware key is not communicatively coupled to the hardware key interface or if a hardware key is communicatively coupled to the hardware key interface and the hardware key is not authorized.

25. The apparatus of claim 24, wherein the output indicates that communications should be permitted over the debug interface if a hardware key is communicatively coupled to the hardware key interface and the hardware key is authorized.

26. A system comprising:

means for determining when a debug device external to the system is attempting to communicate over a debug interface of the system; and

means for, when the debug device external to the system is attempting to communicative over the debug interface, determining if an authorized hardware key is communicatively coupled to the system and preventing communications from occurring over the debug interface between the debug device and the system if an authorized hardware key is not communicatively coupled to the system.

27. The system of claim 26, further comprising means for, when the debug device external to the system is attempting to communicative over the debug interface, permitting communications over the debug interface between the debug device and the system if an authorized hardware key is communicatively coupled to the system.

28. The system of claim 26, further comprising means for, when the debug device external to the system is attempting to communicative over the debug interface, considering an intrusion attempt to have occurred if an authorized hardware key is not communicatively coupled to the system.

29. A hardware key comprising:

an interface to communicatively couple the hardware key to a system;

wherein when the hardware key is communicatively coupled to the system, the hardware key outputs information used by the system to determine whether to permit communications to occur over a debug interface.

30. The hardware key of claim 29, wherein the information comprises a key bit stream.

31. The hardware key of claim 30, wherein the hardware key uses a polynomial to generate the key bit stream, wherein the information further comprises the polynomial.

32. The hardware key of claim 31, wherein the system determines if the information received from the hardware key comprises the key bit stream in order to determine whether to permit communication over the debug interface.

33. The hardware key of claim 32, further comprising a linear shift feedback register to generate the key bit stream, wherein the polynomial comprises a seed value, a length of the linear shift feedback register, and one or more taps of the linear shift feedback register.

34. The hardware key of claim 32, wherein, while the hardware key is communicatively coupled to the system, the hardware key periodically communicates a new polynomial to the system for use in generating the key bit stream.

35. The hardware key of claim 32, further comprising a clock to output a clock signal for use by the system to clock data over the debug interface.