Efficient charge transferring in CMOS imagers

• US 20070045681A1
• Filed: 08/30/2005
• Published: 03/01/2007
• Est. Priority Date: 08/30/2005
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Hong, Sungkwon, Agranov, Gennadiy, Mauritzson, Richard, Hong, Canaan
• Granted Patent: US 7,829,832 B2
• Time in Patent Office: Days
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14654 Blooming suppression
• CPC Class Codes: H04N 23/70 Circuitry for compensating brightness variation in the scene
• CPC Class Codes: H04N 23/741 by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
• CPC Class Codes: H04N 25/575 with a response composed of multiple slopes
• CPC Class Codes: H04N 25/621 for the control of blooming
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

Methods for operating a pixel cell include efficient transferring of photo-charges using multiple pulses to a transistor transfer gate during a charge integration period for an associated photosensor. The pixel cell can be operated with efficient transfer characteristics in either normal or high dynamic range (HDR) mode. The high dynamic range can be realized by either operating an optional HDR transistor or by fluctuating the voltage applied to a reset gate.

Claims

1. A method of operating a pixel cell comprising:

initiating an integration period for the pixel cell during which a photosensor collects photo-charges;

applying a first signal level to a transfer gate of the pixel cell during the integration period such that a first amount of photo-charges are transferred from the photosensor to a storage region; and

applying a second signal level to the transfer gate during the integration period such that a second amount of photo-charges are transferred from the photosensor to the storage region, said second signal level being a pulsed signal.

2. The method of claim 1, wherein said first signal level represents an intermediate level, between zero and a full turn on voltage for the gate of the transfer transistor.

3. The method of claim 2, wherein said first signal level is at a power supply voltage for the pixel cell.

4. The method of claim 1, further comprising the act of applying a first reset signal level to a reset gate of the pixel cell during the integration period.

5. The method of claim 4, further comprising the act of decreasing the reset level from the first reset level to a second reset level during the integration period.

6. The method of claim 5, wherein the act of applying a pulsed second signal level to the transfer gate occurs just before the act of decreasing the reset signal level.

7. The method of claim 4, further comprising the acts of:

decreasing the voltage applied to the reset gate from the first reset signal level to a second reset signal level during the integration period; and

decreasing the voltage of the second reset signal level to a third signal level during the integration period.

8. The method of claim 7, wherein the transfer gate signal applied to the transfer gate is pulsed before each act of decreasing the reset signal level.

9. The method of claim 8, wherein both of the transfer gate signals and the reset gate signals are returned to ground at an end of the integration period.

10. A high dynamic range method of operation for a pixel cell comprising the acts of

transferring charges located at a photosensor to an anti-blooming storage region;

applying a first reset voltage to a reset gate;

decreasing the voltage applied to the reset gate at pre-determined intervals during an integration period for the pixel to increase a potential barrier between a charge storage region and a drain region; and

pulsing a voltage applied to a transfer gate of a transfer transistor during the integration period to decrease the potential barrier between said photosensor and said charge storage region.

11. The method of claim 10, wherein the act of pulsing a voltage applied to the transfer gate is done just prior to the act of decreasing the voltage applied to the reset gate.

12. The method of claim 10, further comprising the acts of:

returning the signal applied to the anti-blooming gate to ground; and

at the end of the integration period, returning the signal applied to the transfer gate to ground.

13. The method of claim 12, wherein the off-state voltage signal for the anti-blooming gate represents a higher voltage than the off-state voltage signal applied to the transfer gate.

14. The method of claim 10, further comprising the act of maintaining an intermediate voltage applied to the transfer gate between the high voltage pulses.

15. The method of claim 14, wherein the intermediate voltage is between zero and a power supply voltage for the pixel cell.

16. The method of claim 10, further comprising the act of maintaining a ground voltage applied to the transfer gate between the high voltage pulses.

17. An imager device comprising:

a pixel array comprising a plurality of pixel cells each comprising;

a photosensor for generating photo-charges during an integration period;

a storage region for storing the generated photo-charges; and

a transfer gate for transferring charges from the photosensor to the storage region, wherein the transfer gate is adapted to receive a first signal and at least one pulsed second signal during the integration period; and

a control circuit for controlling the signals applied to the transfer gates.

18. The imager of claim 17, wherein the imager is a CMOS imager.

19. The imager of claim 17, wherein the pixel cells are operated by the control circuit globally.

20. The imager of claim 17, wherein the pixel cells are operated by the control circuit on a rolling basis.

21. The imager of claim 17, further comprising an anti-blooming transistor gate connected on one side to the photosensor and at another side to a drain region for receiving excess charges from said photosensor.

22. The imager of claim 17, further comprising a reset gate that is adapted to receive at least one reset level during the integration period.

23. The imager of claim 22, wherein the controller causes a pulsed signal to be applied to the transfer gate each time a new reset level is to be applied to the reset gate during the integration period.

24. A method of operating a pixel cell, said method comprising:

lowering a potential barrier between a photosensor and a storage region by applying a first voltage level to a transfer transistor gate during an integration period so as to allow photo-charges at the photosensor to flow to the storage region; and

lowering the potential barrier between the photosensor and the storage region further by applying a second voltage level to the transfer transistor gate during the integration period, wherein the second voltage level is higher than the first voltage level.

25. The method of claim 24, wherein the first voltage level is ground potential.

26. The method of claim 24, wherein the second voltage level is at least equal to a power supply voltage for the pixel cell.

27. The method of claim 26, wherein the second voltage level is more than the power supply voltage for the pixel cell.

28. The method of claim 24, wherein the second voltage level is less than a power supply voltage for the pixel cell.

29. The method of claim 24, further comprising the act of increasing the dynamic range of the pixel cell by decreasing a voltage applied to a reset gate of a reset transistor during the integration period.

30. The method of claim 29, wherein the act of lowering the potential barrier between the photosensor and the storage region further by applying a second voltage level to the transfer transistor gate during the integration period is repeated a predetermined number of times.