Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures

• US 20070045697A1
• Filed: 08/31/2005
• Published: 03/01/2007
• Est. Priority Date: 08/31/2005
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Hsu, Louis, Mandelman, Jack
• Application Number:
  US11/216,386
• Publication Number:
  US 20070045697A1
• Time in Patent Office: Days
• US Class Current: 257/301
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.

Claims

1. A semiconductor structure comprising:

a semiconductor wafer including a semiconductor substrate, a semiconductor layer including a plurality of semiconductor bodies, and a buried dielectric layer separating said semiconductor substrate from said semiconductor body;

a plurality of memory cells built in an array on said semiconductor wafer, each of said memory cells including a storage capacitor and an access device, and said access device including a vertical channel defined in one of the semiconductor bodies and a gate configured to switch current flow through said vertical channel to said storage capacitor; and

a body contact in said buried dielectric layer, said body contact adapted to electrically couple one of said semiconductor bodies with said semiconductor substrate.

2. The semiconductor structure of claim 1 further comprising:

an insulator-filled trench electrically isolating a pair of said memory cells from adjacent memory cells in said array, said body contact extending substantially through said dielectric layer between said pair of said memory cells.

3. The semiconductor structure of claim 2 further comprising:

a first word line electrically coupled with said gate of one of said pair of said memory cells; and

a second word line positioned between said pair of said memory cells, said body contact being aligned vertically with said second word line.

4. The semiconductor structure of claim 1 wherein said buried dielectric layer has a first stoichiometry, and said body contact further comprises a region of said buried dielectric layer with a second stoichiometry that differs from the first stoichiometry.

5. The semiconductor structure of claim 4 wherein said region of said buried oxide layer is enriched atomically in an element of said buried dielectric layer.

6. The semiconductor structure of claim 4 wherein said buried dielectric layer is a buried oxide layer and the first stoichiometry includes silicon and oxygen, and the second stoichiometry of said region of said buried oxide layer is enriched atomically in silicon.

7. The semiconductor structure of claim 6 wherein the second stoichiometry of said region of said buried oxide layer includes about 1 atomic percent to about 6 atomic percent of silicon in excess of the first stoichiometry of said buried oxide layer.

8. The semiconductor structure of claim 7 wherein the first stoichiometry of said buried oxide layer is a stoichiometric ratio of silicon and oxygen.

9. The semiconductor structure of claim 1 wherein each of said memory cells comprises an eight square feature dynamic random access memory (DRAM) memory cell.

10. A method for forming a semiconductor structure in a semiconductor wafer including a semiconductor substrate, a semiconductor layer including a plurality of semiconductor bodies, and a buried dielectric layer separating the semiconductor substrate from the semiconductor layer, the method comprising:

forming a plurality of trenches in the semiconductor wafer;

building a plurality of vertical memory cells each in a corresponding one of the trenches; and

forming a body contact that extends substantially through the buried dielectric layer and electrically couples one of the semiconductor bodies with the semiconductor substrate.

11. The method of claim 10 wherein forming the body contact further comprising:

implanting ions that stop in a region of the buried dielectric layer between two of the trenches to define the at least one body contact.

12. The method of claim 11 wherein the buried dielectric layer is a buried oxide layer containing silicon and oxygen in a first stoichiometry, and implanting ions further comprises:

implanting silicon ions into the region of buried oxide layer to provide a second stoichiometry in the implanted region that differs from the first stoichiometry.

13. The method of claim 12 wherein an implanted dose of silicon ions is sufficient to sufficient to provide a second stoichiometry including about 1 atomic percent to about 6 atomic percent of silicon in excess of the first stoichiometry of the buried oxide layer.

14. The method of claim 10 the vertical memory cells further include a first vertical memory cell and a second vertical memory cell adjacent to the first vertical memory cell, and further comprising:

forming an insulating layer on the semiconductor body;

building a plurality of word lines on the semiconductor wafer including a first word line on the insulating layer between the first and second memory cells and electrically isolated from the first and second memory cells; and

removing a portion of the first word line to provide a body contact opening that exposes an area of the insulating layer overlying a region in the buried dielectric layer in which the body contact is subsequently formed.

15. The method of claim 14 wherein forming the at least one body contact further comprises:

implanting ions into the region in the buried dielectric layer through the body contact opening.

16. The method of claim 15 wherein the implanted ions penetrate through the insulating layer area and an area of the semiconductor body registered vertically with the insulating layer area to reach the buried dielectric layer region.

17. The method of claim 16 wherein implanting ions further comprises:

selecting a kinetic energy of the implanted ions such that the implanted ions stop predominantly in the buried dielectric layer underlying the removed portion of the first word line to define the at least one body contact.

18. The method of claim 14 wherein the word lines further include a second word line connected with an access device of the first vertical memory cell and a third word line connected with an access device of the second vertical memory cell, the second and third word lines electrically isolated from the first word line.

19. The method of claim 10 wherein each of the vertical memory cells including a storage capacitor and an access device with a vertical channel defined in the semiconductor body and a gate configured to switch current flow through the vertical channel to the storage capacitor.