Semiconductor structures with body contacts and fabrication methods thereof

• US 20070045698A1
• Filed: 08/31/2005
• Published: 03/01/2007
• Est. Priority Date: 08/31/2005
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Divakaruni, Ramachandra, Cheng, Kangguo, Mandelman, Jack
• Application Number:
  US11/216,395
• Publication Number:
  US 20070045698A1
• Time in Patent Office: Days
• US Class Current: 257/301
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.

Claims

1. A semiconductor structure comprising:

a semiconductor wafer including a semiconductor substrate, a semiconductor layer with a plurality of semiconductor bodies, and a buried dielectric layer separating said semiconductor substrate from said semiconductor layer;

a plurality of memory cells built in an array on said semiconductor wafer, each of said memory cells including a storage capacitor and an access device, and said access device including a vertical channel region defined in one of the semiconductor bodies and a gate configured to switch current flow through said vertical channel region to said storage capacitor; and

a body contact of an electrically conductive material extending through said buried dielectric layer, said body contact having a first end electrically connected with one of said semiconductor bodies and a second end electrically connected with said semiconductor substrate.

2. The semiconductor structure of claim 1 further comprising:

an insulator-filled trench electrically isolating a pair of said memory cells from adjacent memory cells in said array, said body contact extending substantially through said dielectric layer between said pair of said memory cells.

3. The semiconductor structure of claim 2 further comprising:

a first word line electrically coupled with said gate of one of said pair of said memory cells; and

a second word line positioned between said pair of said memory cells, said body contact being aligned vertically with said second word line.

4. The semiconductor structure of claim 1 further comprising:

a via extending through said semiconductor body and said buried dielectric layer and into said semiconductor substrate, said via being partially filled by said body contact; and

a sidewall spacer with said via and separating said body contact from the corresponding one of said semiconductor bodies.

5. The semiconductor structure of claim 4 wherein said access device of each of said memory cells further includes a source/drain region electrically coupled with said storage capacitor, and said sidewall spacer is positioned between said source/drain region and said body contact.

6. The semiconductor structure of claim 5 wherein said sidewall spacer comprises an isolation collar of an insulating material.

7. The semiconductor structure of claim 6 wherein said body contact includes a first region and a second region spaced within said via by said isolation collar from said first region.

8. The semiconductor structure of claim 7 wherein said body contact includes a third region electrically coupling said first and second regions and positioned within said via inside said isolation collar.

9. The semiconductor structure of claim 1 wherein said semiconductor body is formed from a semiconductor material, and further comprising:

a via extending through the corresponding one of said semiconductor bodies and the buried dielectric layer and extending into the semiconductor substrate, said body contact being positioned within said via;

an insulating layer within said via and overlying said body contact; and

a plug of said semiconductor material within said via and separated from said body contact by said insulating layer, said plug filling said via such that said semiconductor body has an interface with the semiconductor body.

10. The semiconductor structure of claim 9 wherein said access device of each of said memory cells further includes a source/drain region electrically coupled by said vertical channel region with said storage capacitor when said gate is switched to permit current flow through said vertical channel region to said storage capacitor, said source/drain region extending into said semiconductor body and into said plug.

11. The semiconductor structure of claim 1 wherein each of said memory cells comprises an eight square feature dynamic random access memory (DRAM) memory cell.

12. A method for forming a semiconductor structure in a semiconductor wafer including a semiconductor substrate, a semiconductor layer with a plurality of semiconductor bodies, and a buried dielectric layer separating the semiconductor substrate from the semiconductor layer, the method comprising:

building a plurality of vertical memory cells each in a corresponding one of a plurality of trenches in the semiconductor wafer;

forming a via extending through one of the semiconductor bodies and the buried dielectric layer and extending into the semiconductor substrate; and

at least partially filling the via with a plug of an electrically conductive material that extends through the buried dielectric layer to define a body contact having a first end electrically connected with the semiconductor body and a second end electrically connected with the semiconductor substrate.

13. The method of claim 12 wherein the vertical memory cells further include a first vertical memory cell and a second vertical memory cell adjacent to the first vertical memory cell, and further comprising:

forming an insulating layer on the semiconductor body; and

building a plurality of word lines on the semiconductor wafer including a first word line on the insulating layer between the first and second memory cells and electrically isolated from the first and second memory cells, the first word line aligned vertically with the body contact.

14. The method of claim 13 wherein the plurality of word lines further includes a second word line connected with an access device of the first vertical memory cell and a third word line connected with an access device of the second vertical memory cell, the second and third word lines electrically isolated from the first word line.

15. The method of claim 12 further comprising:

forming a sidewall spacer within the via that separates the body contact from the semiconductor body.

16. The method of claim 15 wherein forming the sidewall spacer further comprises:

forming an epitaxial layer on a portion of the semiconductor body bordering the via.

17. The method of claim 15 wherein forming the sidewall spacer further comprises:

forming an isolation collar of an insulating material on a portion of the semiconductor body bordering the via and surrounding a portion of the body contact.

18. The method of claim 12 further comprising:

forming an insulating layer in the via above the body contact; and

forming a plug of semiconductor material within the via and on the insulating layer, the plug having an interface within said via with the semiconductor body.

19. The method of claim 18 wherein each of the vertical memory cells includes an access device with a first source/drain region and a storage capacitor electrically coupled by the first source/drain region with the access device, and further comprising:

introducing a dopant into the semiconductor body and the plug of semiconductor material to define a second source/drain region for the access device of each of the vertical memory cells.

20. The method of claim 18 wherein the body contact is doped with a concentration of a p-type dopant and the semiconductor material in the plug is doped with a concentration of an n-type dopant.

21. The method of claim 12 wherein each of the vertical memory cells includes a storage capacitor and an access device with a vertical channel region defined in one of the semiconductor bodies and a gate configured to switch current flow through the vertical channel region to the storage capacitor.

22. The method of claim 12 wherein forming the via further comprises:

etching the via into the semiconductor wafer.