Gate pattern of semiconductor device and method for fabricating the same

• US 20070045724A1
• Filed: 02/24/2006
• Published: 03/01/2007
• Est. Priority Date: 08/25/2005
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lim, Kwan-Yong, Sung, Min-Gyu, Kim, Hyun-Jung, Chun, Yun-Seok
• Application Number:
  US11/361,378
• Publication Number:
  US 20070045724A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A gate pattern of a semiconductor device and a method for fabricating the same are provided. The gate pattern includes a substrate with a trench, a gate insulation layer, a first gate electrode layer and a second gate electrode layer. The gate insulation layer is formed over the substrate with the trench. The first gate electrode layer is buried into the trench not to be projected above the gate insulation layer. The second gate electrode layer is formed over the first gate electrode layer and has a predetermined portion contacting the first gate electrode layer.

Claims

1. A gate pattern of a semiconductor device, comprising:

a substrate with a trench;

a gate insulation layer formed over the substrate with the trench;

a first gate electrode layer buried into the trench not to be projected above the gate insulation layer disposed over the substrate where the trench is not formed; and

a second gate electrode layer formed over the first gate electrode layer and having a predetermined portion contacting the first gate electrode layer.

2. The gate pattern of claim 1, wherein the first gate electrode layer is recessed to a predetermined depth at a contact region between the first gate electrode layer and the second gate electrode layer, so that the first gate electrode layer contacts the second gate electrode layer.

3. The gate pattern of claim 2, wherein a width of the contact region between the first gate electrode layer and the second gate electrode layer is smaller than that of the first gate electrode layer by a size ranging from approximately 5 nm to approximately 10 nm.

4. The gate pattern of claim 3, wherein the first gate electrode layer includes one of polysilicon and poly-Si_xGe_1-x, where x representing an atomic ratio ranges from approximately 0.01 to approximately 0.99.

5. The gate pattern of claim 1, wherein the second gate electrode layer includes one of a metal layer and a silicide layer.

6. The gate pattern of claim 5, wherein the second gate electrode layer includes one selected from the group consisting of WSi_x, TiSi_x, NiSi_x, CoSi_x, TaSi_x, MoSi_x, HfSi_x, ZrSi_x, PtSi_x, W/WN, W/W—

Si—

N/WSi_x, W/TiN/TiSi_x, W/Ti—

Si—

N/TiSi_x, Ti—

Si—

N, Ti—

Al—

N, Ta—

Si—

N, MoN, HfN, TaN and TiN, where x representing an atomic ratio ranges from approximately 1.0 to approximately 3.0.

7. The gate pattern of claim 1, further comprising an etch stop layer formed over the gate insulation layer disposed over the substrate where the trench is not formed and extending over a portion of the first gate electrode layer not contacting the second gate electrode layer.

8. The gate pattern of claim 7, wherein the etch stop layer includes one selected from the group consisting of an oxide-based material, a nitride-based material and a combination thereof.

9. The gate pattern of claim 8, wherein the oxide-based material is one selected from the group consisting of SiO₂, SiO_xN_y, HfO₂, HfSi_xO_y and HfSi_xO_yN_z, where x, y and z representing atomic ratios range from approximately 0.1 to approximately 3.0, and the nitride-based material includes silicon nitride (Si₃N₄).

10. The gate pattern of claim 7, wherein the gate insulation layer includes one selected from the group consisting of SiO₂, SiO_xN_y, HfO₂, HfSi_xO_y and HfSi_xO_yN_z, wherein x, y and z representing atomic ratios range from approximately 0.1 to approximately 3.0.

11. The gate pattern of claim 7, further comprising a hard mask formed over the second gate electrode layer.

12. A method for fabricating a gate pattern of a semiconductor device, comprising:

preparing a substrate including a trench;

forming a gate insulation layer over the substrate including the trench;

forming a first gate electrode layer buried into the trench not to be projected above the gate insulation layer disposed over the substrate where the trench is not formed; and

forming a second gate electrode layer over the first gate electrode layer to make a predetermined portion of the second gate electrode layer contacting the first gate electrode layer.

13. The method of claim 12, wherein the forming of the first gate electrode layer buried into the trench includes:

forming a first gate electrode layer over the gate insulation layer to fill the trench; and

etching the first gate electrode layer through one of an etch-back process and a chemical mechanical polishing (CMP) process up to an upper portion of the gate insulation layer disposed over the substrate in which the trench is not formed.

14. The method of claim 13, after the etching of the first gate electrode layer up to the upper portion of the gate insulation layer disposed over the substrate where the trench is not formed, further including recessing a portion of the first gate electrode layer corresponding to a contact region in which the first gate electrode layer contacts the second gate electrode layer to a predetermined depth.

15. The method of claim 14, wherein the contact region has a width smaller than the first gate electrode layer by a size ranging from approximately 5 nm to approximately 10 nm.

16. The method of claim 12, after the forming of the first gate electrode layer, further including:

forming an etch stop layer over the first gate electrode layer and the gate insulation layer; and

exposing a predetermined portion of the first gate electrode layer by etching a predecided portion of the etch stop layer.

17. The method of claim 16, wherein the etch stop layer includes one selected from the group consisting of an oxide-based material, a nitride-based material and a combination thereof.

18. The method of claim 17, where the oxide-based material is one selected from the group consisting of SiO₂, SiO_xNy_y, HfO₂, HfSi_xO_y and HfSi_xO_yN_z, wherein x, y and z representing atomic ratios range from approximately 0.1 to approximately 3.0, and the nitride-based material is formed by using Si₃N₄.

19. The method of claim 18, wherein the first gate electrode layer includes one of polysilicon and poly-Si_xGe_1-x, where x representing an atomic ratio ranges from approximately 0.01 to approximately 0.99.

20. The method of claim 12, wherein the second gate electrode layer includes one of a metal layer and a silicide layer.

21. The method of claim 20, wherein the second gate electrode layer includes one selected from the group consisting of WSi_x, TiSi_x, NiSi_x, CoSi_x, TaSi_x, MoSi_x, HfSi_x, ZrSi_x, PtSi_x, W/WN, W/W—

Si—

N/WSi_x, W/TiN/TiSi_x, W/Ti—

Si—

N/TiSi_x, Ti—

Si—

N, Ti—

Al—

N, Ta—

Si—

N, MoN, HfN, TaN and TiN, where x representing an atomic ratio ranges from approximately 1.0 to approximately 3.0.

22. The method of claim 21, wherein the forming of the second gate electrode layer includes:

forming the second gate electrode layer over the first gate electrode layer and the etch stop layer; and

etching a predetermined portion of the second gate electrode layer.

23. The method of claim 22, wherein the etching of the predetermined portion of the second gate electrode layer uses a hard mask scheme.

24. The method of claim 21, wherein the gate insulation layer includes one selected from the group consisting of SiO₂, SiO_xN_y, HfO₂, HfSi_xO_y and HfSi_xO_yN_z, where x, y and z representing atomic ratios range from approximately 0.1 to approximately 3.0.