Semiconductor device with recessed L-shaped spacer and method of fabricating the same

• US 20070045754A1
• Filed: 08/30/2005
• Published: 03/01/2007
• Est. Priority Date: 08/30/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Thei, Kong-Beng, Chuang, Harry, Chen, Chung-Long
• Granted Patent: US 7,298,011 B2
• Time in Patent Office: Days
• US Class Current: 257/412
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A semiconductor device with a recessed L-shaped spacer and a method for fabricating the same. A recessed L-shaped spacer includes a vertical portion and a horizontal portion. The vertical portion is disposed on lower sidewalls of a conductor pattern, exposing upper sidewalls thereof. A top spacer is on the L-shaped spacer, wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is at least about 2:1.

Claims

1. A semiconductor device with a recessed L-shaped spacer, comprising:

a conductor pattern;

an L-shaped spacer comprising a vertical portion and a horizontal portion, the vertical portion disposed on lower sidewalls of the conductor pattern, exposing upper sidewalls thereof; and

a top spacer on the L-shaped spacer, wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is at least about 2;

1.

2. The semiconductor device of claim 1, wherein the conductor pattern is an interconnection pattern.

3. The semiconductor device of claim 1, wherein the conductor pattern is a gate pattern.

4. The semiconductor device of claim 1, wherein the conductor pattern comprises polysilicon.

5. The semiconductor device of claim 1, wherein the width ratio of the vertical portion of the L-shaped spacer to the top spacer is about 2-4:

1.

6. The semiconductor device of claim 1, wherein a ratio of the width of the vertical portion to the height of the exposed upper sidewalls of the conductor pattern is about 1-2:

1.

7. The semiconductor device of claim 1, wherein the horizontal portion is undercut under the top spacer, wherein a ratio of the width of the undercut to the height of the horizontal portion is less than about 0.3.

8. The semiconductor device of claim 1, wherein the L-shaped spacer and the top spacer are formed of materials having etch selectivity with respect to each other.

9. The semiconductor device of claim 1, wherein the L-shaped spacer comprises silicon oxide and the top spacer comprises silicon nitride or silicon oxynitride.

10. The semiconductor device of claim 1, wherein the conductor pattern is silicided.

11. A semiconductor device with a recessed L-shaped spacer, comprising:

a gate pattern;

an L-shaped spacer comprising a vertical portion and a horizontal portion, the vertical portion being on lower sidewalls of the conductor pattern, exposing upper sidewalls thereof;

a top spacer on the L-shaped spacer, protruding above the same, thereby providing a gap between the top spacer and the upper sidewalls of the conductor pattern; and

source/drain regions in the substrate oppositely adjacent to the gate pattern,

wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is at least about 2;

1, and the width of the vertical portion to the height of the exposed upper sidewalls is about 1-2;

1.

12. The semiconductor device of claim 11, wherein the gate pattern comprises a gate electrode on a gate dielectric.

13. The semiconductor device of claim 11, wherein width ratio of the vertical portion of the L-shaped spacer the top spacer is about 2-4:

1.

14. The semiconductor device of claim 11, wherein the horizontal portion is undercut under the top spacer, wherein a ratio of the width of the undercut to the height of the horizontal portion is less than about 0.3.

15. The semiconductor device of claim 11, wherein the L-shaped spacer and the top spacer are formed of materials having etch selectivity with respect to each other.

16. The semiconductor device of claim 11, wherein the L-shaped spacer comprises silicon oxide and the top spacer comprises silicon nitride or silicon oxynitride.

17. The semiconductor device of claim 11, wherein the gate pattern and the source/drain regions are silicided.

18. The semiconductor device of claim 11, further comprising an etch stop layer and an interlevel dielectric layer overlying the gate pattern and the substrate.

19. The semiconductor device of claim 11, wherein the width of the vertical portion is about 350-450 Å

and the width of the top spacer is about 100-200 Å

.

20. The semiconductor device of claim 11, wherein about 200-400 Å

of the gate pattern is exposed by the vertical portion of the L-shaped spacer.