Passive elements in MRAM embedded integrated circuits

• US 20070045759A1
• Filed: 08/31/2005
• Published: 03/01/2007
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chung, Young, Baird, Robert, Grynkewich, Gregory, Durlam, Mark, Salter, Eric
• Granted Patent: US 7,264,985 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.

Claims

1. An integrated circuit device, comprising:

a substrate;

a plurality of front end layers formed on the substrate;

a plurality of back end layers formed over the plurality of front end layers;

a magnetic random access memory (“

MRAM”

) cell formed in the plurality of back end layers; and

,

a passive device formed, at least in part, in one of the plurality of back end layers where at least part of the MRAM cell is formed.

2. The device of claim 1, further comprising at least one additional circuit component on the substrate, the at least one additional circuit component being formed below the passive elements.

3. The device of claim 1 wherein the passive device is a resistor.

4. The device of claim 1 wherein the passive device is a capacitor.

5. The device of claim 3 wherein the resistor comprises a resistor element formed in a metal local interconnect layer.

6. The device of claim 3 wherein the resistor comprises a resistor element formed in a bottom electrode of a magnetic tunnel junction layer (MMTJ layer).

7. The device of claim 3 wherein the resistor comprises a resistor element formed in a magnetic tunnel junction layer.

8. The device of claim 7 wherein the resistor element comprises a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the two ferromagnetic layers, wherein the resistance of the resistor element can be set at a high state when the magnetization in the first ferromagnetic layer is anti-parallel to the magnetization in the second ferromagnetic layer and set to a low state when the magnetization in first ferromagnetic layer is parallel to the magnetization in second ferromagnetic layer.

9. The device of claim 7 wherein the resistor element can be shorted by applying excessive voltage to the resistor element of the magnetic tunnel junction layer.

10. The device of claim 4 wherein the capacitor comprises a top electrode formed in a metal global interconnect layer, a bottom electrode formed in a metal local interconnect level and a dielectric layer formed between the top electrode and the bottom electrode.

11. The device of claim 4 wherein the capacitor comprises a top electrode formed in an metal local interconnect level a bottom electrode formed in a bottom electrode of a magnetic tunnel junction layer and a dielectric layer formed between the top electrode and the bottom electrode.

12. The device of claim 4 wherein the capacitor comprises a top electrode formed in a bottom electrode of a magnetic tunnel junction layer (MMTJ layer), a bottom electrode formed in a metal digital kine level and a dielectric layer formed between the top electrode and the bottom electrode.

13. A method of forming an integrated circuit device, said method comprising:

forming, on front end layers of the device, at least one power component;

forming, on the front end layers of the device, a MRAM circuit;

forming, on the back end layers, a MRAM cell; and

forming, on back end layers, a passive device having a feature formed in a backend layer where a feature of the MRAM cell is found.

14. The method of claim 13 wherein the step of forming, on back end layers, a passive device further comprises:

forming a resistor comprising at least one resistor element on a back end layer on which a feature of the MRAM cell is fabricated.

15. The method of claim 13 wherein the step of forming, on back end layers, a passive device further comprises forming a capacitor comprising a top electrode, a bottom electrode and a dielectric between the top electrode and the bottom electrode formed on back end layers, wherein at least one of the backend layers where the capacitor is found is associated with a feature of the MRAM cell.

16. The method of claim 14 wherein the step of forming a resistor further comprises forming a resistor comprising a resistor element formed on a magnetic tunnel junction layer, the resistor element comprising an first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the two ferromagnetic layers, wherein the resistance of the resistor element can be set at a high state when the magnetization in the first ferromagnetic layer is anti-parallel to the magnetization in the second ferromagnetic layer and set to a low state when the magnetization in the first ferromagnetic layer is parallel to the magnetization in second ferromagnetic layer.

17. The method of claim 14 wherein the step of forming a resistor further comprises forming a resistor having a resistance, the resistor comprising a plurality of resistor elements, a portion of the plurality of resistor elements comprising a resistor element formed on a Magnetic Tunnel Junction layer and wherein at least one of the portion of the plurality of resistor elements can be shorted to change the resistance of the resistor.

18. An integrated circuit device comprising:

a substrate;

a plurality of first end layers formed over the substrate;

a magnetoresistive random access memory (MRAM) control circuit formed, at least partially, in the plurality of first end layers;

one or more power components formed in the plurality of first end layers;

a plurality of back end layers formed over the front end layers;

a MRAM cell formed in the plurality of back end layers, the MRAM cell coupled to the MRAM control circuit, the MRAM cell comprising;

at least one digit line;

at least one bit line; and

a magnetic tunnel junction core coupled between the at least one digit line and the at least one bit line; and

at least one passive device formed in the plurality of backend layers, wherein at least part of the passive device is fabricated when at least a portion of the MRAM cell is fabricated.

19. An integrated circuit device according to claim 18 wherein the passive device is a resistor.

20. An integrated circuit device according to claim 18 wherein the passive device is a capacitor.