Semiconductor device having substrate-driven field-effect transistor and schottky diode and method of forming the same

• US 20070045765A1
• Filed: 08/25/2005
• Published: 03/01/2007
• Est. Priority Date: 08/25/2005
• Status: Active Grant

• Current Assignee: Flextronics International USA Incorporated (Flex, Ltd.)
• Original Assignee: Flextronics International USA Incorporated (Flex, Ltd.)
• Inventors: Brar, Berinder, Ha, Wonill
• Granted Patent: US 7,285,807 B2
• Time in Patent Office: Days
• US Class Current: 257/481
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device including a substrate driven field-effect transistor with a lateral channel and a parallel-coupled Schottky diode, and a method of forming the same. In one embodiment, the substrate driven field-effect transistor of the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof, and a lateral channel above the conductive substrate. The substrate driven field-effect transistor also includes a second contact above the lateral channel and an interconnect that connects the lateral channel to the conductive substrate operable to provide a low resistance coupling between the first contact and the lateral channel. The semiconductor device also includes a Schottky diode parallel-coupled to the substrate driven field-effect transistor. A first and second terminal of the Schottky diode are couplable to the first and second contacts, respectively, of the substrate drive field-effect transistor.

Claims

1. A semiconductor device, comprising:

a substrate driven field-effect transistor, including;

a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof,

a lateral channel above said conductive substrate,

a second contact above said lateral channel, and

an interconnect that connects said lateral channel to said conductive substrate operable to provide a low resistance coupling between said first contact and said lateral channel; and

a Schottky diode parallel-coupled to said substrate driven field-effect transistor.

2. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor further comprises a buffer layer interposed between said conductive substrate and said lateral channel.

3. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor further comprises an isolation layer interposed between said conductive substrate and said lateral channel.

4. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor further comprises a spacer layer interposed between said conductive substrate and said lateral channel.

5. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor further comprises a barrier layer interposed between said conductive substrate and said lateral channel.

6. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor further comprises a barrier layer interposed between said lateral channel and said second contact.

7. The semiconductor device as recited in claim 1 wherein said lateral channel is a first lateral channel and said substrate driven field-effect transistor further comprises a second lateral channel above said first lateral channel and a modulation doped spacer layer interposed between said first and second lateral channels.

8. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor further comprises a recess layer interposed between said lateral channel and said second contact.

9. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor further comprises an etch-stop layer interposed between said lateral channel and said second contact.

10. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor further comprises first and second source/drain contact layers interposed between said lateral channel and said second contact.

11. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor further comprises a gate located in a gate recess interposed between said lateral channel and said second contact.

12. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor further comprises a drain post interposed between said lateral channel and said second contact.

13. The semiconductor device as recited in claim 1 wherein said conductive substrate is formed from gallium arsenide.

14. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor further comprises an isolation layer and a barrier layer interposed between said conductive substrate and said second contact configured at least in part to form an intrinsic body diode within said semiconductor device.

15. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor further comprises a buffer layer formed of an alternating aluminum-gallium arsenide/gallium arsenide (“

AlGaAs/GaAs”

) super-lattice buffer interposed between said conductive substrate and said lateral channel.

16. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor further comprises a modulation doped barrier layer formed from aluminum gallium-arsenide (“

AlGaAs”

) interposed between said conductive substrate and said lateral channel.

17. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor further comprises a buffer layer, an isolation layer and a barrier layer interposed between said conductive substrate and said lateral channel configured to form at least in part back-to-back diodes within said semiconductor device.

18. The semiconductor device as recited in claim 1 wherein said lateral channel is formed from indium gallium arsenide.

19. The semiconductor device as recited in claim 1 wherein said lateral channel is pseudomorphic.

20. The semiconductor device as recited in claim 1 wherein said interconnect is located in a via formed through said semiconductor device down to said conductive substrate.

21. The semiconductor device as recited in claim 1 wherein said interconnect has a metal layer on horizontal and semi-horizontal surfaces thereof and is plated with a metal material.

22. The semiconductor device as recited in claim 1 wherein said substrate driven field-effect transistor is an enhancement mode device.

23. The semiconductor device as recited in claim 1 wherein said Schottky diode comprises a Schottky interconnect coupled to a Schottky contact.

24. The semiconductor device as recited in claim 1 wherein said Schottky diode comprises a Schottky contact coupled to said interconnect.

25. The semiconductor device as recited in claim 1 wherein said Schottky diode comprises first and second terminals coupled to said first and second contacts, respectively.

26. A semiconductor device, comprising:

a substrate having a source contact covering a substantial portion of a bottom surface thereof;

a first buffer layer formed over said substrate;

an isolation layer formed over said first buffer layer;

a first spacer layer formed over said isolation layer;

a second buffer layer formed over said first spacer layer;

a first barrier layer formed over said second buffer layer;

a second spacer layer formed over said first barrier layer;

a first lateral channel formed over said second spacer layer;

a third spacer layer formed over said first lateral channel;

a fourth spacer layer formed over said third spacer layer;

a second lateral channel formed over said fourth spacer layer;

a fifth spacer layer formed over said second lateral channel;

a sixth spacer layer formed over said fifth spacer layer;

a third lateral channel formed over said sixth spacer layer;

a seventh spacer layer formed over said third lateral channel;

a second barrier layer formed over said seventh spacer layer;

a recess layer formed over said second barrier layer;

an etch-stop layer formed over said recess layer;

first and second source/drain contact layers formed over said etch-stop layer;

a source interconnect that connects said first, second and third lateral channels to said substrate operable to provide a low resistance coupling between said source contact and said first, second and third lateral channels;

a gate located in a gate recess formed though said first and second source/drain contact layers, said etch-stop and said recess layer;

a dielectric layer formed over said gate, and said first and second source/drain contact layers;

a drain post located in a drain via formed through said dielectric layer and over said first and second source/drain contact layers;

a drain contact coupled to said drain post; and

;

a Schottky diode having a first terminal coupled to said source contact and a second terminal coupled to said drain contact.

27. The semiconductor device as recited in claim 26 wherein said substrate is formed from gallium arsenide.

28. The semiconductor device as recited in claim 26 wherein said isolation layer forms an intrinsic body diode at least in part with said first barrier layer.

29. The semiconductor device as recited in claim 26 wherein said second buffer layer is an alternating aluminum-gallium arsenide/gallium arsenide (“

AlGaAs/GaAs”

) super-lattice buffer.

30. The semiconductor device as recited in claim 26 wherein said first barrier layer is formed from aluminum gallium-arsenide (“

AlGaAs”

).

31. The semiconductor device as recited in claim 26 wherein said first barrier layer is modulation doped.

32. The semiconductor device as recited in claim 26 wherein said isolation layer forms back-to-back diodes at least in part with said first buffer layer and said first barrier layer.

33. The semiconductor device as recited in claim 26 wherein said first, second and third lateral channels are formed from indium gallium arsenide.

34. The semiconductor device as recited in claim 26 wherein said first, second and third lateral channels are pseudomorphic.

35. The semiconductor device as recited in claim 26 wherein said third, fifth and seventh spacer layers are modulation doped.

36. The semiconductor device as recited in claim 26 wherein said source interconnect is located in a source via formed through said semiconductor device down to said substrate.

37. The semiconductor device as recited in claim 26 wherein said source interconnect has a metal layer on horizontal and semi-horizontal surfaces thereof.

38. The semiconductor device as recited in claim 26 wherein said source interconnect is plated with a metal material.

39. The semiconductor device as recited in claim 26 wherein said gate is formed by multiple layers.

40. The semiconductor device as recited in claim 26 wherein said drain post is plated with a metal material.

41. The semiconductor device as recited in claim 26 wherein said source and drain contacts are formed by a metallic alloy.

42. The semiconductor device as recited in claim 26 wherein said semiconductor device is an enhancement mode device.

43. The semiconductor device as recited in claim 26 wherein said seventh spacer layer is modulation doped to a selected level to provide an enhancement mode device.

44. The semiconductor device as recited in claim 26 wherein said Schottky diode further comprises a Schottky contact and Schottky interconnect coupled to said source contact.

45. The semiconductor device as recited in claim 26 wherein said Schottky diode further comprises a Schottky contact coupled to said source interconnect.

46. A semiconductor device, comprising:

a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof;

a lateral channel above said conductive substrate;

a second contact above said lateral channel;

an interconnect that connects said lateral channel to said conductive substrate operable to provide a low resistance coupling between said first contact and said lateral channel;

an intrinsic body diode operable to provide a conductive path between said first and second contacts; and

a Schottky diode operable to provide a conductive path between said first and second contacts.

47. The semiconductor device as recited in claim 46 wherein said intrinsic body diode is formed at least in part by an isolation layer and a barrier layer above said conductive substrate.

48. The semiconductor device as recited in claim 46 further comprising a spacer layer and a barrier layer interposed between said conductive substrate and said lateral channel.

49. The semiconductor device as recited in claim 46 further comprising a modulation doped spacer layer and a barrier layer interposed between said lateral channel and said second contact.

50. The semiconductor device as recited in claim 46 further comprising a recess layer, an etch-stop layer and first and second source/drain contact layers interposed between said lateral channel and said second contact.

51. The semiconductor device as recited in claim 46 further comprising a gate located in a gate recess interposed between said lateral channel and said second contact.

52. The semiconductor device as recited in claim 46 further comprising a drain post interposed between said lateral channel and said second contact.

53. The semiconductor device as recited in claim 46 further comprising a buffer layer formed of an alternating aluminum-gallium arsenide/gallium arsenide (“

AlGaAs/GaAs”

) super-lattice buffer interposed between said conductive substrate and said lateral channel.

54. The semiconductor device as recited in claim 46 further comprising a modulation doped barrier layer formed from aluminum gallium-arsenide (“

AlGaAs”

) interposed between said conductive substrate and said lateral channel.

55. The semiconductor device as recited in claim 46 further comprising a buffer layer, an isolation layer and a barrier layer interposed between said conductive substrate and said lateral channel configured to form at least in part back-to-back diodes within said semiconductor device.

56. The semiconductor device as recited in claim 46 wherein said lateral channel is pseudomorphic.

57. The semiconductor device as recited in claim 46 wherein said interconnect is located in a via formed through said semiconductor device down to said conductive substrate, said interconnect having a metal layer on horizontal and semi-horizontal surfaces thereof and being plated with a metal material.

58. The semiconductor device as recited in claim 46 wherein said lateral channel is a first lateral channel and further comprising a second lateral channel above said first lateral channel.

59. The semiconductor device as recited in claim 46 wherein said Schottky diode comprises a Schottky contact coupled to said interconnect.

60. The semiconductor device as recited in claim 46 wherein said Schottky diode comprises first and second terminals coupled to said first and second contacts, respectively.