STRUCTURE OF AN ULTRA-THIN WAFER LEVEL STACK PACKAGE

• US 20070045806A1
• Filed: 10/27/2006
• Published: 03/01/2007
• Est. Priority Date: 02/05/2004
• Status: Abandoned Application

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsuan, Min-Chih
• Application Number:
  US11/553,480
• Publication Number:
  US 20070045806A1
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure of an ultra-thin wafer level stack package is provided. A method for manufacturing the structure includes providing a first wafer having a plurality of base chips thereon, selectively binding the first wafer to a second substrate, lapping the first wafer to reduce its thickness, dicing the lapped first wafer, bonding a plurality stack chips to each base chip and packaging the base chip with the bonded stack chips to form an IC package. Thus, each IC package comprises at least a base chip and a stack chip. The IC package has a size almost identical to the base chip and a thickness a little larger than the combined thickness of the base chip and the stack chip. If a known good die inspection of the base chips and stack chips are carried out prior to wafer level packaging, overall yield of the IC package is increased.

Claims

1. A structure of a stack package, comprising:

an independent chip set, obtained by dicing an selectively adhered wafer, wherein the selectively adhered wafer comprises;

a first wafer and a second substrate bonded to the first wafer through a plurality of adhesives, wherein the first wafer has a plurality of base chips thereon, a distance between the first wafer and the second substrate is equal to a thickness of the adhesive; and

wherein each independent chip set comprises a base chip and a portion of the second substrate.

2. The structure of claim 1, wherein the independent chip set is obtained by cutting a second surface of the first wafer of the selectively adhered wafer, wherein a depth of cutting is greater than a thickness of the first wafer but smaller than the total thickness of the first wafer and the adhesive;

and

cutting a second surface of the second substrate of the selectively adhered wafer, wherein a depth of cutting is greater than a thickness of the second substrate but smaller than the total thickness of the second substrate and the adhesive.

3. The structure of claim 1, further comprises a stack chip bonded to the base chip of the independent chip set.

4. The structure of claim 1, further comprises a plurality of stack chips bonded to the base chip of the independent chip set.

5. The structure of claim 1, wherein the first wafer has a thickness between about 30 μ

m to 250 μ

m.

6. The structure of claim 1, wherein the first wafer has a thickness between about 30 μ

m to 80 μ

m.

7. The structure of claim 1, wherein the second substrate comprises a plurality of chips, and a position of each of the chips is matched with the first wafer.

8. The structure of claim 1, wherein the second substrate comprises a glass substrate.

9. The structure of claim 1, wherein the second substrate comprises a silicon wafer substrate.

10. The structure of claim 1, wherein the second substrate comprises a plastic substrate.

11. The structure of claim 1, wherein the second substrate comprises an acrylic substrate.

12. The structure of claim 1, wherein the second substrate comprises a polymer substrate.

13. The structure of claim 1, wherein the second substrate is fabricated using a transparent material.

14. The structure of claim 1, wherein the second substrate is fabricated using a non-transparent material.