Method for forming a double embossing structure

• US 20070045855A1
• Filed: 07/24/2006
• Published: 03/01/2007
• Est. Priority Date: 07/22/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Chou, Chiu-Ming, Chou, Chien-Kang, Lo, Hsin-Jung
• Granted Patent: US 7,960,269 B2
• Time in Patent Office: Days
• US Class Current: 257/771
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05083 Three-layer arrangements
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/1147 : using a lift-off mask
• CPC Class Codes: H01L 2224/13021 : the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/13023 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48644 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48844 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10271 : Silicon-germanium [SiGe]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.

Claims

1. A method for fabricating a circuitry component, comprising

depositing a first metal layer over a substrate;

forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer;

depositing a second metal layer over said first metal layer exposed by said first opening;

removing said first pattern-defining layer;

forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer;

depositing a third metal layer over said second metal layer exposed by said second opening;

removing said second pattern-defining layer;

after said removing said second pattern-defining layer, removing said first metal layer not under said second metal layer; and

after said removing said first metal layer, forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.

2. The method of claim 1, wherein said depositing said second metal layer comprises depositing a copper layer with a thickness of between 1 and 20 microns over said first metal layer exposed by said first opening.

3. The method of claim 1, wherein said depositing said second metal layer comprises depositing a gold layer with a thickness of between 1 and 20 microns over said first metal layer exposed by said first opening.

4. The method of claim 1, wherein said depositing said second metal layer comprises electroplating.

5. The method of claim 1, wherein said depositing said third metal layer comprises depositing a gold layer with a thickness of between 1 and 30 microns over said second metal layer exposed by said second opening.

6. The method of claim 1, wherein said depositing said third metal layer comprises depositing a tin-containing layer with a thickness of between 10 and 150 microns over said second metal layer exposed by said second opening.

7. The method of claim 1, wherein said depositing said third metal layer comprises electroplating.

8. A method for fabricating a circuitry component, comprising

depositing a first metal layer over a substrate;

forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer;

depositing a second metal layer over said first metal layer exposed by said first opening;

removing said first pattern-defining layer;

forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer;

depositing a third metal layer over said second metal layer exposed by said second opening; and

removing said second pattern-defining layer, wherein said third metal layer is used to be wirebonded thereto.

9. The method of claim 8, wherein said depositing said second metal layer comprises depositing a copper layer with a thickness of between 1 and 20 microns over said first metal layer exposed by said first opening.

10. The method of claim 8, wherein said depositing said second metal layer comprises depositing a gold layer with a thickness of between 1 and 20 microns over said first metal layer exposed by said first opening.

11. The method of claim 8, wherein said depositing said second metal layer comprises electroplating.

12. The method of claim 8, wherein said depositing said third metal layer comprises depositing a gold layer with a thickness of between 1 and 30 microns over said second metal layer exposed by said second opening.

13. The method of claim 8, wherein said depositing said third metal layer comprises electroplating.

14. A method for fabricating a circuitry component, comprising

depositing a first metal layer over a substrate;

forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer;

depositing a second metal layer over said first metal layer exposed by said first opening;

removing said first pattern-defining layer;

forming a polymer layer over said second metal layer and part of said first metal layer; and

removing said first metal layer not under said second metal layer and not under said polymer layer.

15. The method of claim 14, after forming said polymer layer, further comprising:

forming a second pattern-defining layer over said first metal layer, a second opening in said second pattern-defining layer exposing said second metal layer;

depositing a third metal layer over said second metal layer exposed by said second opening; and

removing said second pattern-defining layer, followed by said removing said first metal layer.

16. The method of claim 15, wherein said depositing said third metal layer comprises depositing a gold layer with a thickness of between 1 and 30 microns over said second metal layer exposed by said second opening.

17. The method of claim 15, wherein said depositing said third metal layer comprises depositing a tin-containing layer with a thickness of between 10 and 150 microns over said second metal layer exposed by said second opening.

18. The method of claim 15, wherein said depositing said third metal layer comprises electroplating.

19. The method of claim 14, wherein said depositing said second metal layer comprises depositing a copper layer with a thickness of between 1 and 20 microns over said first metal layer exposed by said first opening.

20. The method of claim 14, wherein said depositing said second metal layer comprises depositing a gold layer with a thickness of between 1 and 20 microns over said first metal layer exposed by said first opening.