In-loop duty corrector delay-locked loop for multiphase clock generation

• US 20070046345A1
• Filed: 08/24/2005
• Published: 03/01/2007
• Est. Priority Date: 08/24/2005
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Micrel Incorporated (Microchip Technology Incorporated)
• Inventors: Tai, Gwo-Chung, Hui, Kin
• Granted Patent: US 7,330,059 B2
• Time in Patent Office: Days
• US Class Current: 327/158
• CPC Class Codes: H03K 2005/00039 having four transistors serially
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence

Abstract

A delay-locked loop (DLL) employs an in-loop duty cycle corrector (DCC) to provide accurate multiphase clock generation with 50% duty cycle. Each delay cell can advantageously provide both delay and duty cycle correction functionality. In one embodiment, delay correction can precede duty cycle correction. The bandwidths of the DCC and the DLL can differ by a factor of a decade to achieve fast and stable operation.

Claims

1. A delay-locked loop (DLL) including:

a plurality of serially-connected delay cells, wherein each delay cell includes an internal duty cycle correction loop;

delay correction circuitry for providing a control voltage to the plurality of delay cells via a DLL feedback loop; and

a lock detector that activates the duty cycle correction loop of each delay cell based on the control voltage.

2. The DLL of claim 1, wherein each delay cell includes:

a delay circuit for receiving an input clock signal and generating an output clock signal;

a delay adjustment circuit for receiving a signal on the DLL feedback loop and modifying the input clock signal;

a duty cycle corrector for receiving the output clock signal and generating an offset signal; and

a duty cycle adjustment circuit for receiving the offset signal and modifying the output clock signal.

3. The DLL of claim 2, wherein the delay circuit and the delay adjustment circuit include a first transconductor (601), the duty cycle corrector includes a second transconductor (605), and the duty cycle adjustment circuit includes a third transconductor (608).

4. The DLL of claim 3, wherein the first, second, and third transconductors are fully differential.

5. The DLL of claim 3, wherein the first transconductor is fully differential, the second transconductor is differential input and single-ended output, and the third transconductor is single input and differential output.

6. The DLL of claim 1, wherein the delay correction circuitry includes a first capacitor to determine a first bandwidth of the DLL feedback loop, wherein the delay cell includes a second capacitor to determine a second bandwidth of the duty cycle correction loop, and the second bandwidth is at least 10×

the first bandwidth.

7. The DLL of claim 1, wherein the delay cell includes a capacitor to determine a bandwidth of the duty cycle correction loop, wherein the capacitor provides a dominant pole in the duty cycle correction loop.

8. The DLL of claim 1, wherein each delay cell includes:

a first transconductor for receiving a signal on the DLL feedback loop and modifying a delay of the input clock signal, wherein an output clock signal is based on an output of the first transconductor;

a second transconductor for receiving the output clock signal and sensing a duty cycle offset in the output clock signal; and

a third transconductor for receiving a voltage offset signal corresponding to the duty cycle offset and modifying the output of the first transconductor until a duty cycle of the output clock signal is 50%.

9. The DLL of claim 8, wherein the first, second, and third transconductors are fully differential.

10. The DLL of claim 8, wherein the first transconductor is fully differential, the second transconductor is differential input and single-ended output, and the third transconductor is single input and differential output.

11. The DLL of claim 8, wherein the delay correction circuitry includes a first capacitor to determine a first bandwidth of the DLL feedback loop, wherein the delay cell includes a second capacitor to determine a second bandwidth of the duty cycle correction loop, and the second bandwidth is at least 10×

the first bandwidth.

12. The DLL of claim 8, wherein the delay cell includes a capacitor to determine a bandwidth of the duty cycle correction loop, wherein the capacitor provides a dominant pole in the duty cycle correction loop.

19. The delay cell of claim 8, wherein the first transconductor is fully differential, the second transconductor is differential input and single-ended output, and the third transconductor is single input and differential output.

13. A delay cell for a delay-locked loop (DLL), the delay cell including:

means for delaying an input signal to the delay cell based on a DLL feedback loop; and

means for modifying a duty cycle of an output signal of the delay cell based on an internal loop of the delay cell.

14. A delay cell for a delay-locked loop (DLL), the delay cell including:

a first transconductor that delays an input signal to the delay cell based on a DLL feedback loop; and

a duty cycle correction circuit for modifying a duty cycle of an output signal of the delay cell based on an internal loop of the delay cell.

15. The delay cell of claim 14, wherein the duty cycle correction circuit includes:

a second transconductor coupled to an output of the first transconductor;

a capacitor connected to an output of the second transconductor; and

a third transconductor connected to the output of the second transconductor and the capacitor,

wherein an output of the first transconductor forms the output signal of the delay cell or combined outputs of the first and third transconductors form the output signal of the delay cell.

16. The delay cell of claim 15, wherein the output of the first transconductor forms the output signal of the delay cell during an inactive duty cycle correction (DCC) state of the delay cell, and wherein the combined outputs of the first and third transconductors form the output signal of the delay cell during an active DCC state of the delay cell.

17. The delay cell of claim 15, wherein the inactive DCC state precedes the active DCC state.

18. The delay cell of claim 15, wherein the first, second, and third transconductors are fully differential.

20. The delay cell of claim 15, wherein the capacitor provides a high bandwidth compared to that of the DLL feedback loop.

21. The delay cell of claim 15, wherein the capacitor provides a dominant pole in the internal loop.

22. A method of generating multiple phases of a clock in a delay-locked loop (DLL), the method comprising:

using a plurality of delay cells to delay a clock received by the DLL, each delay cell outputting one phase of the clock;

performing delay correction using a DLL feedback loop, the DLL feedback loop connected to each delay cell; and

performing duty cycle correction within each delay cell of the DLL, thereby minimizing duty cycle offset propagation in the DLL.

23. The method of claim 22, wherein performing delay correction precedes performing duty cycle correction.

24. The method of claim 22, wherein performing duty cycle correction includes providing a 50% duty cycle.

25. The method of claim 24, wherein the clock received by the DLL is not approximately 50% duty cycle.

26. The method of claim 24, wherein the number of the plurality of delay cells is half the number of standard delay cells.