Bias circuit having transistors that selectively provide current that controls generation of bias voltage
First Claim
1. A bias circuit which generates a bias voltage, comprising:
- a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node, wherein the first MOS transistor has a first ON-state resistance;
a second MOS transistor coupled in parallel with the first MOS transistor, wherein the second MOS transistor has a second ON-state resistance which is lower than the first ON-state resistance of the first MOS transistor;
a resistance circuit coupled between the voltage dividing node and a second reference voltage terminal; and
a voltage generator coupled with the voltage dividing node, the voltage generator outputting the bias voltage in dependence upon an electrical potential on the voltage dividing node, wherein the resistance circuit is a constant-voltage circuit.
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Abstract
A bias circuit, which generates a bias voltage, has a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node and a second MOS transistor coupled in parallel with the first MOS transistor. The first MOS transistor may have a first ON-state resistance, and the second MOS transistor may have a second ON-state resistance which is lower than the first ON-state resistance. Furthermore, the bias circuit has a resistance circuit coupled between the voltage dividing node and a second reference voltage terminal and a voltage generator coupled with the first node. The voltage generator outputs the bias voltage in dependence upon an electrical potential on the voltage dividing node.
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Citations
48 Claims
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1. A bias circuit which generates a bias voltage, comprising:
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a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node, wherein the first MOS transistor has a first ON-state resistance;
a second MOS transistor coupled in parallel with the first MOS transistor, wherein the second MOS transistor has a second ON-state resistance which is lower than the first ON-state resistance of the first MOS transistor;
a resistance circuit coupled between the voltage dividing node and a second reference voltage terminal; and
a voltage generator coupled with the voltage dividing node, the voltage generator outputting the bias voltage in dependence upon an electrical potential on the voltage dividing node, wherein the resistance circuit is a constant-voltage circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A bias circuit which generates a bias voltage, comprising:
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a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node, wherein the first MOS transistor has a first ON-state resistance;
a second MOS transistor coupled in parallel with the first MOS transistor, wherein the second MOS transistor has a second ON-state resistance which is lower than the first ON-state resistance of the first MOS transistor;
a resistance circuit coupled between the voltage dividing node and a second reference voltage terminal; and
a voltage generator coupled with the voltage dividing node, the voltage generator outputting the bias voltage in dependence upon an electrical potential on the voltage dividing node, wherein the voltage generator includes an output terminal from which the bias voltage is output, a first current mirror circuit coupled between the first reference voltage terminal and the output terminal, wherein the first current mirror circuit includes two P-type MOS transistors, and a second current mirror circuit coupled between the output terminal and the second reference voltage terminal, wherein the second current mirror circuit includes two N-type MOS transistors.
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17. A bias circuit which generates a bias voltage, comprising:
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a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node, wherein the first MOS transistor has a first gate width and a first gate length;
a second MOS transistor coupled in parallel with the first MOS transistor, wherein the second MOS transistor has a second gate width and a second gate length, and wherein a ratio of the second gate width to the second gate length is greater than a ratio of the first gate width to the first gate length;
a resistance circuit coupled between the voltage dividing node and the second reference voltage terminal; and
a voltage generator coupled with the voltage dividing node, the voltage generator outputting the bias voltage in dependence upon an electrical potential on the voltage dividing node, wherein the resistance circuit is a constant-voltage circuit. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A bias circuit which generates a bias voltage, comprising:
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a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node, wherein the first MOS transistor has a first gate width and a first gate length;
a second MOS transistor coupled in parallel with the first MOS transistor, wherein the second MOS transistor has a second gate width and a second gate length, and wherein a ratio of the second gate width to the second gate length is greater than a ratio of the first gate width to the first gate length;
a resistance circuit coupled between the voltage dividing node and the second reference voltage terminal; and
a voltage generator coupled with the voltage dividing node, the voltage generator outputting the bias voltage in dependence upon an electrical potential on the voltage dividing node, wherein the voltage generator includes an output terminal from which the bias voltage is output, a first current mirror circuit coupled between the first reference voltage terminal and the output terminal, wherein the first current mirror circuit includes two P-type MOS transistors, and a second current mirror circuit coupled between the output terminal and the second reference voltage terminal, wherein the second current mirror circuit includes two N-type MOS transistors.
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33. A bias circuit which generates first and second bias voltages, comprising:
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a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node, wherein the first MOS transistor is capable of passing a first ON-state current therethrough;
a second MOS transistor coupled in parallel with the first MOS transistor, wherein the second MOS transistor is capable of passing a second ON-state current therethrough, the second ON-state current being greater than the first ON-state current;
a resistance circuit coupled between the voltage dividing node and the second reference voltage terminal; and
a voltage generator coupled with the voltage dividing node, the voltage generator outputting the first and second bias voltages in dependence upon an electrical potential generated on the voltage dividing node, wherein the resistance circuit is a constant-voltage circuit. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. A bias circuit which generates first and second bias voltages, comprising:
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a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node, wherein the first MOS transistor is capable of passing a first ON-state current therethrough;
a second MOS transistor coupled in parallel with the first MOS transistor, wherein the second MOS transistor is capable of passing a second ON-state current therethrough, the second ON-state current being greater than the first ON-state current;
a resistance circuit coupled between the voltage dividing node and the second reference voltage terminal; and
a voltage generator coupled with the voltage dividing node, the voltage generator outputting the first and second bias voltages in dependence upon an electrical potential generated on the voltage dividing node, wherein the voltage generator includes first and second output terminals from which the first and second bias voltages are respectively output, a first current mirror circuit coupled between the first reference voltage terminal and the first output terminal, wherein the first current mirror circuit includes two P-type MOS transistors, and a second current mirror circuit coupled between the second output terminal and the second reference voltage terminal, wherein the second current mirror circuit includes two N-type MOS transistors.
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Specification