High Sensitivity RFID TAG Integrated Circuits

• US 20070046369A1
• Filed: 07/22/2006
• Published: 03/01/2007
• Est. Priority Date: 07/22/2005
• Status: Abandoned Application

• Current Assignee: Innurvation IP LLC
• Original Assignee: Innurvation IP LLC
• Inventors: Schober, Robert, Opris, Ion, Krummenacher, Francois
• Application Number:
  US11/459,339
• Publication Number:
  US 20070046369A1
• Time in Patent Office: Days
• US Class Current: 330/7
• CPC Class Codes: G06K 19/0707 the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation G06K19/0702 takes precedence
• CPC Class Codes: G06K 19/0713 the arrangement including a power charge pump
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2200/162 FETs are biased in the weak inversion region
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/70 Charge amplifiers
• CPC Class Codes: H03F 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A method and apparatus for an ultra-high sensitivity, low cost, passive (no battery) low-power energy harvesting data transmitting circuit energy, such as a RFID (Radio Frequency IDentification) tag integrated circuit “chip.” By using combinations of special purpose design enhancements, the low-power energy harvesting passive data transmitting circuit, such as the RFID tag chip, operates in the sub-microwatt power range. The chip power should be derived from a low-microwatt per square centimeter RF field radiated to the RFID tag antenna from the tag reader (interrogator) or derived from a suitable low signal source, such as a sonic transducer (e.g., a piezoelectric transducer or a low level DC source, such as a bimetallic or chemical source).

Claims

1. A charge pump circuit comprising:

a first diode-connected transistor having a first electrode connected with a first power source and a second electrode connected with a first node;

a first capacitor connected between the first node and a second power source;

a second diode-connected transistor having a first electrode connected with the first node and a second electrode connected with a second node; and

a second capacitor connected between the second node and the first power source,

wherein at least one of the first and second diode-connected transistors has a substantially zero threshold voltage.

2. The charge pump circuit of claim 1, further comprising:

a third diode-connected transistor having a first electrode connected with the second node and a second electrode connected with a third node;

a third capacitor connected between the third node and the second power source;

a fourth diode-connected transistor having a first electrode connected with the third node and a second electrode connected with a fourth node; and

a fourth capacitor connected between the fourth node and the first power source.

3. The charge pump circuit of claim 2, wherein the first, second, third, and fourth diode-connected transistors have respective channel lengths adjusted according to their respective maximum hold off voltages.

4. The charge pump circuit of claim 1, wherein at least one of the first and second diode-connected transistors has a body electrode electrically coupled to the first power source or the second node.

5. The charge pump circuit of claim 4, wherein the body electrode is electrically coupled to the first power source when the first power source has a voltage level higher than the second node, and wherein the body electrode is electrically coupled to the second node when the second node has a voltage level higher than the first power source.

6. The charge pump circuit of claim 1, wherein the first power source is a reference node and the second power source is an alternating input node.

7. The charge pump circuit of claim 1, further comprising a plurality of terminals adapted to receive an alternative voltage signal, wherein the first power source is electrically coupled to one of the plurality of terminals, and wherein the second power source is electrically coupled to another one of the plurality of terminals.

8. The charge pump circuit of claim 7, wherein the second node is adapted to provide a substantially constant voltage.

9. The charge pump circuit of claim 1, wherein the charge pump circuit is incorporated within a Radio Frequency IDentification (RFID) tag having a modulator electrically coupled between the first and second power sources, the modulator being adapted to modify an impedance between the first and second power sources.

10. The charge pump circuit of claim 1, wherein each of the first and second diode-connected transistors is a native MOS transistor.

11. The charge pump circuit of claim 1, wherein each of the first and second diode-connected transistors has a substantially zero threshold voltage.

12. The charge pump circuit of claim 1, wherein the charge pump circuit is incorporated within a Radio Frequency IDentification (RFID) tag, and wherein the RFID tag comprises another charge pump circuit electrically coupled to the first power source and a third power source to increase a differential charge pump output voltage level.

13. The charge pump circuit of claim 1, wherein the charge pump circuit is incorporated within a Radio Frequency IDentification (RFID) tag and has a first storage capacitance, wherein the RFID tag comprises another charge pump electrically coupled to the first and second power sources, and wherein the another charge pump has a second storage capacitance lower than the first storage capacitance to detect data from signals provided to the first and second power sources.

14. The charge pump circuit of claim 13, wherein the RFID tag further comprises a current comparator electrically coupled to the charge pump circuit and another current comparator electrically coupled to the another charge pump circuit to detect the data from the signals provided to the first and second power sources.

15. The charge pump circuit of claim 1, wherein each of the first and second diode-connected transistors has a body electrode electrically coupled to the first power source or the second node.

16. A low-power energy harvesting passive data transmitting circuit comprising:

a primary inductor;

a charge pump having an input capacitance and an alternating input terminal, the input terminal being connected between the primary inductor and the input capacitance; and

a modulator electrically coupled to the charge pump through the primary inductor to back scatter an energy,

wherein the energy is supplied to the primary inductor, and

wherein the primary inductor has an inductance selected to resonate with the input capacitance at a frequency of a signal applied to the alternative input terminal to boost a voltage supplied to the alternating input terminal of the charge pump.

17. The low-power energy harvesting passive data transmitting circuit of claim 16, wherein the primary inductor includes a part of an antenna of a Radio Frequency IDentification (RFID) tag.

18. The low-power energy harvesting passive data transmitting circuit of claim 16, wherein the primary inductor includes a part of an antenna of a Radio Frequency (RF) device.

19. The low-power energy harvesting passive data transmitting circuit of claim 16, wherein a part of the primary inductor is incorporated within a chip of a Radio Frequency IDentification (RFID) tag.

20. The low-power energy harvesting passive data transmitting circuit of claim 16, wherein a part of the primary inductor is incorporated within a chip of a Radio Frequency (RF) device.

21. A low-power energy harvesting passive data transmitting circuit comprising:

a first controlled current source connected with a second controlled current source via a common control node and a common power sink node; and

a ring oscillator adapted to be supplied with a current from the first controlled current source via a supplied node connected between the first controlled current source and the ring oscillator.

22. The low-power energy harvesting passive data transmitting circuit of claim 21, further comprising:

a grounded current adjuster connected with the second controlled current source via a resistance terminal node connected between the second controlled current source and the grounded resistor; and

an amplifier having an inverting input, a non-inverting input, and an output,

wherein the inverting input node is connected with the supply node, the non-inverting input is connected with the resistance terminal node, and the output is connected with the common control node.

23. The low-power energy harvesting passive data transmitting circuit of claim 22, further comprising:

an auxiliary circuitry connected with the grounded resistor to digitally program a resistance value of the grounded current adjuster to tune an oscillation frequency of the ring oscillator.

24. The low-power energy harvesting passive data transmitting circuit of claim 22, further comprising:

a voltage follower having an input connected with the supply node and an output adapted to supply a subsequent digital circuitry.

25. The low-power energy harvesting passive data transmitting circuit of claim 21, further comprising:

an auxiliary circuitry connected with the first controlled current source to digitally program a current gain value of the first controlled current source to tune an oscillation frequency of the ring oscillator.

26. The low-power energy harvesting passive data transmitting circuit of claim 21, wherein the ring oscillator comprises N number of inverters, and wherein N is an odd number.

27. The low-power energy harvesting passive data transmitting circuit of claim 26, wherein each of the N number of inverters is loaded with an equivalent capacitance CL/N so that the average dynamic current supplied to the N number of inverters is Io=Fo·

CL·

Vo, and wherein Fo is an oscillation frequency of the N number of inverters and Vo is a voltage of the N number of inverters.

28. The low-power energy harvesting passive data transmitting circuit of claim 27, wherein the voltage Vo is less than a sum of a NMOS threshold voltage and a PMOS threshold voltage.

29. The low-power energy harvesting passive data transmitting circuit of claim 27, further comprising a bypass capacitor connected between the supplied node and a ground to filter out a voltage ripple.

30. A method of designing a low-transient power energy harvesting passive data transmitting circuit, the method comprising:

generating a plurality of logic and memory functions to represent a network of the low-transient power energy harvesting passive data transmitting circuit;

minimizing coincident logic transitions including data handling transitions and memory transitions to spread the plurality of logic, data handling, and memory functions with a grey code type logic to reduce peak energy drain; and

designing the low-transient power energy harvesting passive data transmitting circuit to include the network in accordance with the logic, data handling, and memory functions with the minimized coincident logic, data handling, and memory transitions to minimize a power supply ripple of the low-transient power energy harvesting passive data transmitting circuit.

31. A method of designing a low-transient power energy harvesting passive data transmitting circuit, the method comprising:

generating a plurality of self-timed logic functions to represent a network of the low-transient power energy harvesting passive data transmitting circuit; and

designing the low-transient power energy harvesting passive data transmitting circuit to include the network in accordance with the self-timed logic functions to eliminate a clock distribution and reduce an operating voltage of the low-transient power energy harvesting passive data transmitting circuit.

32. A method of designing a low-transient power energy harvesting passive data transmitting circuit, the method comprising:

generating a plurality of low-voltage logic functions to represent a network of the low-transient power energy harvesting passive data transmitting circuit; and

designing the low-transient power energy harvesting passive data transmitting circuit to include the network in accordance with the low-voltage logic functions to reduce an operating voltage of the low-transient power energy harvesting passive data transmitting circuit,

wherein the operating voltage is not greater 800 mV and targeted at 500 mV for typical parameters and operating conditions.

33. The method of claim 32, wherein the operating voltage is regulated by a current-fed ring oscillator circuit.

34. The method of claim 33, wherein the current-fed ring oscillator compensates for parameter variations.

35. The method of claim 33, wherein the designing of the low-transient power energy harvesting passive data transmitting circuit comprises using transistors having threshold voltages to enable to the current-fed ring oscillator to set the operating voltage to below 500 mV and above 200 mV

36. A charge pump circuit comprising:

a first diode-connected transistor having a first electrode connected with a first power source and a second electrode connected with a first node;

a first capacitor connected between the first node and a second power source;

a second diode-connected transistor having a first electrode connected with the first node and a second electrode connected with a second node; and

a second capacitor connected between the second node and the first power source,

wherein at least one of the first and second capacitors is formed using a transistor having a substantially zero threshold voltage.

37. The charge pump circuit of claim 36, wherein the transistor is a native MOS transistor.

38. The charge pump circuit of claim 36, wherein the second capacitor is formed using the transistor, and wherein the first capacitor is not formed using the transistor.

39. The charge pump circuit of claim 36, wherein at least one of the first and second diode-connected transistors has a substantially zero threshold voltage.