PLL circuit with self-selecting variable divide ratio

• US 20070046388A1
• Filed: 09/01/2005
• Published: 03/01/2007
• Est. Priority Date: 09/01/2005
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Inphi Corporation
• Inventors: Sanders, Jeffrey
• Granted Patent: US 7,245,191 B2
• Time in Patent Office: Days
• US Class Current: 331/179
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/107 using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

A PLL circuit provides a self-selecting divide ratio, which is varied as necessary to lock the circuit to a reference clock which may have several possible frequencies, thereby enabling the VCO to employ a type of oscillator having a superior jitter characteristic. The PLL circuit includes a variable divider which divides the VCO output by a divide ratio value provided by a frequency band select circuit, which provides the divide ratio needed to drive the phase difference between the reference and divided clocks toward zero while the VCO clock output operates within a predetermined frequency range. The self-selecting variable divide ratio allows the VCO'"'"'s oscillator to have a narrow output frequency range, thereby allowing the use of an oscillator type with a jitter characteristic which may be low enough to meet the requirements of JEDEC, for example.

Claims

1. A phase-locked loop (PLL) circuit with self-selecting variable divide ratio, comprising:

a voltage-controlled oscillator (VCO) having an input and which produces a clock output having a frequency that varies within a predetermined frequency range with a control voltage applied to said input;

a variable divider having an divide ratio control input and which receives said VCO clock output and divides it by a divide ratio value that varies with a divide ratio control signal applied to said divide ratio control input;

a phase detector which receives a reference clock and said divided-down VCO clock at respective inputs and produces one or more outputs that vary with the difference in phase between said inputs; and

a loop filter which receives at least one of said phase detector outputs and provides said control voltage to said VCO input so as to reduce the difference in phase between said reference clock and said divided-down VCO clock; and

a frequency band select circuit which provides said divide ratio control signal to said variable divider'"'"'s divide ratio control input such that a divide ratio value is selected which enables said phase difference to be driven toward zero with said VCO clock output within said predetermined frequency range.

2. The PLL circuit of claim 1, wherein said VCO is an L-C tank oscillator.

3. The PLL circuit of claim 1, wherein said PLL circuit has a predetermined loop gain specification, said frequency band select circuit arranged to provide said divide ratio control signal such that said PLL circuit'"'"'s loop gain remains within said predetermined loop gain specification.

4. The PLL circuit of claim 3, wherein said loop gain specification is that specified by JEDEC for DDR RAM.

5. The PLL circuit of claim 3, wherein said loop filter is arranged to receive said divide ratio control signal and to vary said control voltage with said divide ratio control signal.

6. The PLL circuit of claim 5, wherein said loop filter comprises a charge pump, said loop filter arranged such that the current produced by said charge pump varies inversely with said divide ratio control signal such that PLL loop bandwidth is constant for all obtainable divide ratio values.

7. The PLL circuit of claim 1, wherein said loop filter is arranged to, in response to a SEARCH signal, output a control voltage to said VCO such that said VCO'"'"'s output frequency is in the middle of said predetermined frequency range.

8. The PLL circuit of claim 7, wherein said frequency band select circuit is arranged to vary said divide ratio control signal under predetermined conditions, and to provide said SEARCH signal to said loop filter when one or more of said predetermined conditions is detected.

9. The PLL circuit of claim 8, wherein said frequency band select circuit is arranged such that one of said predetermined conditions is the application of power to said PLL circuit.

10. The PLL circuit of claim 8, wherein said band select circuit receives said reference clock and said divided-down VCO clock at respective inputs, said reference clock having a frequency f_ref and said divided-down VCO clock having a frequency f_div, said frequency band select circuit arranged such that one of said predetermined conditions is the detection of a difference between f_div and f_ref greater than a predetermined minimum value.

11. The PLL circuit of claim 10, wherein said band select circuit is further arranged to output said divide ratio control signal such that said divide ratio value is decreased if f_div<

f_ref and said divide ratio value is increased if f_div>

f_ref.

12. The PLL circuit of claim 11, wherein said band select circuit is further arranged to:

detect when said divide ratio value is toggling between two adjacent values;

compare the amount of time spent at each of said two adjacent divide ratio values; and

provide the divide ratio control signal to said variable divider'"'"'s divide ratio control input needed to select the divide ratio value at which the greater amount of time is spent.

13. A method of setting a divide ratio for a phase-locked loop circuit which includes a voltage controlled oscillator (VCO) that produces an output clock signal (VCOClk), comprising:

monitoring a reference clock (RefClk) having a frequency f_ref and a clock (DivClk) having a frequency f_div produced by dividing VCOClk by a divide ratio;

detecting a “

cycle slip”

, defined as when a plot of the time difference between the rising edge of RefClk and the rising edge of DivClk versus time passes through zero, said cycle slip being an “

up-slip”

when said plot passes through zero due to f_div>

f_ref and a “

down-slip”

when said plot passes through zero due to f_ref>

f_div;

setting said divide ratio to a mid-ratio value when the number of detected cycle slips exceeds a predetermined minimum number;

incrementing said divide ratio when a predetermined number of consecutive up-slips are detected and decrementing said divide ratio when a predetermined number of consecutive down-slips are detected;

detecting when said divide ratio is being toggled between adjacent values;

detecting when said divide ratio has toggled between adjacent values a predetermined number of times;

selecting the higher of the two divide ratios when said divide ratio has toggled between adjacent values said predetermined number of times and the time that between consecutive up-slips is greater than the time between consecutive down-slips; and

selecting the lower of the two divide ratios when said divide ratio has toggled between adjacent values said predetermined number of times and the time that between consecutive up-slips is less than the time between consecutive down-slips.