Voltage regulation circuit for RFID systems

• US 20070046474A1
• Filed: 08/26/2005
• Published: 03/01/2007
• Est. Priority Date: 08/26/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Balachandran, Ganesh, Barnett, Raymond
• Granted Patent: US 7,538,673 B2
• Time in Patent Office: Days
• US Class Current: 340/572.700
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

A voltage regulation circuit for an RFID circuit having a voltage limiter circuit including a current sensing element for sensing current through the voltage limiter circuit. The voltage limiter generates a limited voltage. A voltage regulator is coupled to the limited voltage for generating a regulated output voltage. The voltage regulator has a dynamic biasing current responsive to an output of the sensing element for increasing bandwidth of the voltage regulator when current in the voltage limiter circuit increases.

Claims

1. A voltage regulation circuit for an RFID circuit comprising:

a voltage limiter circuit having a current sensing element for sensing current through the voltage limiter circuit, the voltage limiter generating a limited voltage;

a voltage regulator coupled to the limited voltage for generating a regulated output voltage, the voltage regulator having a dynamic biasing current responsive to an output of the sensing element for increasing bandwidth of the voltage regulator when current in the voltage limiter circuit increases.

2. The voltage regulation circuit of claim 1 wherein an input voltage to the voltage limiter circuit is a rectified output of an electromagnetic wave signal received by the RFID circuit.

3. The voltage regulation circuit of claim 1 wherein the voltage limiter comprises a plurality of current mirror—

connected transistors, each of the transistors having a weighting resistor in its current path.

4. The voltage regulation circuit of claim 3 wherein each of the transistors has a different value weighting resistor.

5. The voltage regulation circuit of claim 2 wherein the voltage limiter comprises a plurality of current mirror—

connected transistors, each of the transistors having a weighing resistor in its current path.

6. The voltage regulation circuit of claim 2 wherein each of the transistors has a different value weighting resistor.

7. The voltage regulation circuit of claim 1 wherein the current sensing element is a diode—

connected MOS transistor.

8. The voltage regulation circuit of claim 2 wherein the current sensing element is a diode—

connected MOS transistor.

9. The voltage regulation circuit of claim 3 wherein the current sensing element is a diode—

connected MOS transistor.

10. The voltage regulation circuit of claim 4 wherein the current sensing element is a diode—

connected MOS transistor.

11. The voltage regulation circuit of claim 5 wherein the current sensing element is a diode—

connected MOS transistor.

12. The voltage regulation circuit of claim 6 wherein the current sensing element is a diode—

connected MOS transistor.

13. The voltage regulation circuit of claim 1 wherein the circuit is built utilizing deep submicron CMOS technology.

14. The voltage regulation circuit of claim 1 wherein the dynamic bias current is provided by a degenerated transistor.

15. In a RFID transponder, a voltage regulator utilizing deep submicron components comprising:

an error amplifier having a first bias level when an input current is in a first range and a second bias level when the input current exceeds the first range; and

a pass transistor coupled to an output of the error amplifier, whereby the voltage regulator is stable throughout its operating range.

16. The voltage regulator of claim 15 wherein the first bias level is provided by a fixed current level current source and the second bias level is provided by a dynamic current level current source.

17. The voltage regulator of claim 16 wherein the dynamic current source comprises a degenerated transistor.

18. The voltage generator of claim 17 wherein the degenerated transistor is controlled by a current sensor in a voltage limiter stage preceding the voltage regulator.

19. A current limiter comprising:

a diode—

connected transistor coupled between a voltage source and a reference potential;

a plurality of current mirror—

connected transistors connected to the diode—

connected transistor and having a current path between the voltage source and the reference potential; and

the plurality of weighting resistors, each resistor being connected in the current path of one of the plurality of current mirror—

connected transistors.

20. The current limiter of claim 19 wherein each of the weighing resistors has a different resistance valve.