Programming method for NAND EEPROM
First Claim
1. A method of programming memory cells of a NAND architecture memory string, comprising:
- selecting a memory cell of a NAND architecture memory string of a non-volatile memory array; and
selecting and applying a pass voltage to a gate of one or more unselected memory cells of the string based on the position of the selected memory cell in the NAND architecture memory string.
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Accused Products
Abstract
A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines of the memory cell string or array during an programming cycle. In one embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized depending on the placement of the memory cell in the NAND memory cell string. In another embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized to compensate for faster and slower programming word lines/memory cells.
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Citations
51 Claims
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1. A method of programming memory cells of a NAND architecture memory string, comprising:
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selecting a memory cell of a NAND architecture memory string of a non-volatile memory array; and
selecting and applying a pass voltage to a gate of one or more unselected memory cells of the string based on the position of the selected memory cell in the NAND architecture memory string. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of operating a NAND architecture non-volatile memory array, comprising:
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selecting a memory cell in one or more NAND architecture memory cell strings for programming in a selected block of non-volatile memory cells, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line;
applying a program voltage to the word line coupled to the selected memory cells; and
selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings based on the position of the selected memory cells and word line in the one or more NAND architecture memory strings. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A non-volatile NAND architecture memory device comprising:
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a NAND architecture non-volatile memory array having a plurality of memory blocks; and
a control circuit, wherein the control circuit is adapted to program memory cells in a selected memory block of the non-volatile memory array by, selecting a memory cell in one or more NAND architecture memory cell strings for programming in a selected block of non-volatile memory cells, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line, applying a program voltage to the word line coupled to the selected memory cells, and selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings based on the position of the selected memory cells and word line in the one or more NAND architecture memory strings. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A system comprising:
a host coupled to a non-volatile memory device, wherein the non-volatile memory device comprises, a NAND architecture non-volatile memory array having a plurality of blocks;
wherein the system is adapted to program memory cells in a selected block of the non-volatile memory array by, selecting a memory cell in one or more NAND architecture memory cell strings for programming in the selected block of non-volatile memory cells, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line, applying a program voltage to the word line coupled to the selected memory cells, and selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings based on the position of the selected memory cells and word line in the one or more NAND architecture memory strings. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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29. A memory module, comprising:
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at least one NAND architecture memory device containing an array with a plurality of non-volatile memory cells arranged in a plurality of memory blocks;
a housing enclosing the at least one memory device; and
a plurality of contacts configured to provide selective contact between the at least one memory device and a host system;
wherein the memory module is adapted to erase a selected memory block of the at least one memory device by, selecting a memory cell in one or more NAND architecture memory cell strings for programming in a selected block of non-volatile memory cells, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line, applying a program voltage to the word line coupled to the selected memory cells, and selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings based on the position of the selected memory cells and word line in the one or more NAND architecture memory strings. - View Dependent Claims (30)
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31. A memory module, comprising:
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a plurality of contacts; and
two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
wherein at least one of the memory devices comprises;
a NAND architecture non-volatile memory array having a plurality of memory blocks, wherein the memory module is adapted to program memory cells in a selected block of the non-volatile memory array by, selecting a memory cell in one or more NAND architecture memory cell strings for programming in a selected block of non-volatile memory cells, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line, applying a program voltage to the word line coupled to the selected memory cells, and selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings, wherein the pass voltage is selected based on the position of the memory cells and word line in the one or more NAND architecture memory strings selected for programming.
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32. A memory module, comprising:
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a housing having a plurality of contacts; and
one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
wherein the memory module is adapted to program memory cells in a selected block of at least one of the memory devices by, applying a first voltage to a first word line of the block, each first word line coupled to a selected non-volatile memory cell of one or more NAND memory cell strings of the block, applying a second voltage to one or more second word lines of the block, each second word line coupled to one or more unselected non-volatile memory cells of the one or more NAND memory cell strings of the block, and applying a third voltage to a channel of each of the one or more NAND memory cell strings, wherein the second and third voltages are each different from the first voltage and the second voltage is selected based on the position of the first word line in each of the one or more NAND memory cell strings.
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33. A method of programming memory cells in a NAND architecture array of non-volatile memory cells, comprising:
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applying a first voltage to a first word line of a block, each first word line coupled to a selected non-volatile memory cell of one or more NAND memory cell strings of the block;
applying a second voltage to one or more second word lines of the block, each second word line coupled to one or more unselected non-volatile memory cells of the one or more NAND memory cell strings of the block; and
applying a third voltage to a channel of each of the one or more NAND memory cell strings;
wherein the second and third voltages are each different from the first voltage and the second voltage is selected by the position of the first word line in each of the one or more NAND memory cell strings;
wherein the first and third voltages are expected to cause programming of a nominal memory cell of each of the one or more NAND memory cell strings of the block if applied across its word line and the channel. - View Dependent Claims (34, 35, 36)
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37. A method of programming memory cells of a NAND architecture memory string, comprising:
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applying a programming voltage to a first memory cell of a NAND architecture memory string and applying a lower pass voltage to a gate of one or more unselected memory cells of the string;
applying a programming voltage to a middle memory cell of a NAND architecture memory string and applying an average pass voltage to a gate of one or more unselected memory cells of the string; and
applying a programming voltage to a last memory cell of a NAND architecture memory string and applying a higher pass voltage to a gate of one or more unselected memory cells of the string. - View Dependent Claims (38, 39, 40)
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41. A method of programming memory cells of a NAND architecture memory string, comprising:
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applying a programming voltage to a first memory cell of a NAND architecture memory string and applying a lower pass voltage to a gate of one or more unselected memory cells of the string;
applying a programming voltage to a middle memory cell of a NAND architecture memory string, applying an average pass voltage to a gate of one or more unselected memory cells of the string, and applying a very low pass voltage to a gate of the first memory cell of the string, wherein the first memory cell is coupled to a word line that is located adjacent to a source side select gate; and
applying a programming voltage to a last memory cell of a NAND architecture memory string, applying a higher pass voltage to a gate of one or more unselected memory cells of the string, and applying a very low pass voltage to a gate of the first memory cell of the string, wherein the first memory cell is coupled to the word line that is located adjacent to a source side select gate. - View Dependent Claims (42, 43)
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44. A method of operating a NAND architecture non-volatile memory array, comprising:
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selecting a memory cell in one or more NAND architecture memory cell strings for programming in a selected block of non-volatile memory cells, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line;
applying a program voltage to the word line coupled to the selected memory cells; and
selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings based on the position of the selected memory cells and word line in the one or more NAND architecture memory strings, wherein a second pass voltage is applied to a first memory cell of the one of more NAND architecture memory cells if the first memory cell is not currently selected for programming, where the first memory cell is coupled to a WL0 word line that is located adjacent to a source side select gate. - View Dependent Claims (45, 46)
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47. A method of programming two or more memory cells of a NAND architecture memory string, comprising:
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selecting a memory cell of a NAND architecture memory string of a non-volatile memory array to be programmed; and
selecting and applying a pass voltage to a gate of one or more unselected memory cells of the string based on a sequence of programming the two or more memory cells in the NAND architecture memory string. - View Dependent Claims (48, 49, 50, 51)
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Specification