Programming method for NAND EEPROM

• US 20070047314A1
• Filed: 08/31/2005
• Published: 03/01/2007
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi, Goda, Akira, Marquart, Todd
• Granted Patent: US 7,292,476 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines of the memory cell string or array during an programming cycle. In one embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized depending on the placement of the memory cell in the NAND memory cell string. In another embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized to compensate for faster and slower programming word lines/memory cells.

Claims

1. A method of programming memory cells of a NAND architecture memory string, comprising:

selecting a memory cell of a NAND architecture memory string of a non-volatile memory array; and

selecting and applying a pass voltage to a gate of one or more unselected memory cells of the string based on the position of the selected memory cell in the NAND architecture memory string.

2. The method of claim 1, wherein selecting and applying a pass voltage to a gate of one or more unselected memory cells of the string based on the position of the selected memory cell in the NAND architecture memory string further comprises selecting and applying a lower than average pass voltage to a gate of one or more unselected memory cells of the string when a memory cell coupled to an initial word line in the NAND architecture memory string is programmed and selecting and applying a higher than average pass voltage to a gate of one or more unselected memory cells of the string when a memory cell coupled to a final word line in the NAND architecture memory string is programmed.

3. The method of claim 1, wherein selecting and applying a pass voltage to a gate of one or more unselected memory cells of the string based on the position of the selected memory cell in the NAND architecture memory string further comprises selecting and applying a pass voltage to a gate of one or more unselected memory cells of the string based on the position of the selected memory cell in the NAND architecture memory string and the probability of program disturb in an erase block containing the NAND architecture memory string for the selected pass voltage and selected memory cell position being programmed.

4. The method of claim 1, wherein selecting and applying a pass voltage to a gate of one or more unselected memory cells of the string based on the position of the selected memory cell in the NAND architecture memory string further comprises selecting and applying two or more pass voltages to different gates of the one or more unselected memory cells of the string.

5. The method of claim 1, further comprising applying a program voltage a gate of the selected memory cell and coupling one of a program and a program-inhibit voltage to a channel of the NAND architecture memory string.

6. The method of claim 1, further comprising selecting a second pass voltage to apply to one or more second unselected memory cells of the string based on one of a physical or electrical characteristic of the one or more second unselected memory cells, and the position of the one or more second unselected memory cells in the NAND architecture memory string.

7. The method of claim 6, wherein physical or electrical characteristics of the one or more unselected memory cells of the string are one of the program speed of each of the one or more unselected memory cells of the string, the resistance of word lines coupled to each of the one or more unselected memory cells of the string, the coupling ratio of word lines coupled to the gate of each of the one or more unselected memory cells of the string, and the cross-sectional area of word lines coupled to the gate of each of the one or more unselected memory cells of the string.

8. A method of operating a NAND architecture non-volatile memory array, comprising:

selecting a memory cell in one or more NAND architecture memory cell strings for programming in a selected block of non-volatile memory cells, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line;

applying a program voltage to the word line coupled to the selected memory cells; and

selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings based on the position of the selected memory cells and word line in the one or more NAND architecture memory strings.

9. The method of claim 8, wherein selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings based on the position of the selected memory cells and word line in the one or more NAND architecture memory strings further comprises selecting and applying a lower than average pass voltage to the one or more unselected word lines when an initial word line in the one or more NAND architecture memory strings is the selected word line and selecting and applying a higher than average pass voltage to the one or more unselected word lines when a final word line in the one or more NAND architecture memory strings is the selected word line.

10. The method of claim 8, wherein selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings based on the position of the selected memory cells and word line in the one or more NAND architecture memory strings further comprises selecting and applying a lower than average pass voltage to the one or more unselected word lines based on the position of the selected word line in the one or more NAND architecture memory strings and the probability of program disturb in the one or more NAND architecture memory strings for the selected pass voltage and selected word line position being programmed.

11. The method of claim 8, wherein selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings based on the position of the selected memory cells and word line in the one or more NAND architecture memory strings further comprises selecting and applying two or more pass voltages to two or more word lines of the one or more unselected word lines.

12. The method of claim 8, further comprising applying one of a program and a program-inhibit voltage to a channel of each of the NAND architecture memory strings.

13. The method of claim 8, further comprising selecting a second pass voltage to apply to one or more second unselected word lines based on the position of the one or more second unselected word lines in the one or more NAND architecture memory strings.

14. The method of claim 8, further comprising selecting a second pass voltage to apply to one or more second unselected word lines based on one of the program speed of each of the one or more unselected word lines, the resistance of the one or more unselected word lines, the coupling ratio of the one or more unselected word lines, and the cross-sectional area of the one or more unselected word lines.

15. A non-volatile NAND architecture memory device comprising:

a NAND architecture non-volatile memory array having a plurality of memory blocks; and

a control circuit, wherein the control circuit is adapted to program memory cells in a selected memory block of the non-volatile memory array by,

selecting a memory cell in one or more NAND architecture memory cell strings for programming in a selected block of non-volatile memory cells, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line,

applying a program voltage to the word line coupled to the selected memory cells, and

selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings based on the position of the selected memory cells and word line in the one or more NAND architecture memory strings.

16. The non-volatile NAND architecture memory device of claim 15, wherein the control circuit is adapted to select and apply a lower than average pass voltage to the one or more unselected word lines when an initial word line in the one or more NAND architecture memory strings is the selected word line and select and apply a higher than average pass voltage to the one or more unselected word lines when a final word line in the one or more NAND architecture memory strings is the selected word line.

17. The non-volatile NAND architecture memory device of claim 15, wherein the control circuit is adapted to select and apply a lower than average pass voltage to the one or more unselected word lines based on the position of the selected word line in the one or more NAND architecture memory strings and the probability of program disturb in the one or more NAND architecture memory strings for the selected pass voltage and selected word line position being programmed.

18. The non-volatile NAND architecture memory device of claim 15, wherein the control circuit is adapted to select and apply two or more pass voltages to two or more word lines of the one or more unselected word lines.

19. The non-volatile NAND architecture memory device of claim 15, wherein the control circuit is adapted to apply one of a program voltage and a program-inhibit voltage to a channel of each of the NAND architecture memory strings.

20. The non-volatile NAND architecture memory device of claim 15, wherein the control circuit is adapted to select a second pass voltage to apply to one or more second unselected word lines based on the position of the one or more second unselected word lines in the one or more NAND architecture memory strings.

21. The non-volatile NAND architecture memory device of claim 15, wherein the control circuit is adapted to select a second pass voltage to apply to one or more second unselected word lines based on one of the program speed of each of the one or more unselected word lines, the resistance of the one or more unselected word lines, the coupling ratio of the one or more unselected word lines, and the cross-sectional area of the one or more unselected word lines.

22. A system comprising:

a host coupled to a non-volatile memory device, wherein the non-volatile memory device comprises,

a NAND architecture non-volatile memory array having a plurality of blocks;

wherein the system is adapted to program memory cells in a selected block of the non-volatile memory array by,

selecting a memory cell in one or more NAND architecture memory cell strings for programming in the selected block of non-volatile memory cells, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line,

applying a program voltage to the word line coupled to the selected memory cells, and

selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings based on the position of the selected memory cells and word line in the one or more NAND architecture memory strings.

23. The system of claim 22, wherein the host is one of a processor and a memory controller.

24. The system of claim 22, wherein the system is adapted to select and apply a lower than average pass voltage to the one or more unselected word lines when an initial word line in the one or more NAND architecture memory strings is the selected word line and select and apply a higher than average pass voltage to the one or more unselected word lines when a final word line in the one or more NAND architecture memory strings is the selected word line.

25. The system of claim 22, wherein the system is adapted to select and apply a lower than average pass voltage to the one or more unselected word lines based on the position of the selected word line in the one or more NAND architecture memory strings and the probability of program disturb in the one or more NAND architecture memory strings for the selected pass voltage and selected word line position being programmed.

26. The system of claim 22, wherein the system is adapted to select and apply two or more pass voltages to two or more word lines of the one or more unselected word lines.

27. The system of claim 22, wherein the system is adapted to select a second pass voltage to apply to one or more second unselected word lines based on the position of the one or more second unselected word lines in the one or more NAND architecture memory strings.

28. The system of claim 22, wherein the system is adapted to select a second pass voltage to apply to one or more second unselected word lines based on one of the program speed of each of the one or more unselected word lines, the resistance of the one or more unselected word lines, the coupling ratio of the one or more unselected word lines, and the cross-sectional area of the one or more unselected word lines.

29. A memory module, comprising:

at least one NAND architecture memory device containing an array with a plurality of non-volatile memory cells arranged in a plurality of memory blocks;

a housing enclosing the at least one memory device; and

a plurality of contacts configured to provide selective contact between the at least one memory device and a host system;

wherein the memory module is adapted to erase a selected memory block of the at least one memory device by,

selecting a memory cell in one or more NAND architecture memory cell strings for programming in a selected block of non-volatile memory cells, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line,

applying a program voltage to the word line coupled to the selected memory cells, and

selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings based on the position of the selected memory cells and word line in the one or more NAND architecture memory strings.

30. The module of claim 29, further comprising a memory controller coupled to the at least one memory device for controlling operation of each memory device in response to the host system.

31. A memory module, comprising:

a plurality of contacts; and

two or more memory devices, each having access lines selectively coupled to the plurality of contacts;

wherein at least one of the memory devices comprises;

a NAND architecture non-volatile memory array having a plurality of memory blocks,

wherein the memory module is adapted to program memory cells in a selected block of the non-volatile memory array by,

selecting a memory cell in one or more NAND architecture memory cell strings for programming in a selected block of non-volatile memory cells, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line,

applying a program voltage to the word line coupled to the selected memory cells, and

selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings, wherein the pass voltage is selected based on the position of the memory cells and word line in the one or more NAND architecture memory strings selected for programming.

32. A memory module, comprising:

a housing having a plurality of contacts; and

one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;

wherein the memory module is adapted to program memory cells in a selected block of at least one of the memory devices by,

applying a first voltage to a first word line of the block, each first word line coupled to a selected non-volatile memory cell of one or more NAND memory cell strings of the block,

applying a second voltage to one or more second word lines of the block, each second word line coupled to one or more unselected non-volatile memory cells of the one or more NAND memory cell strings of the block, and

applying a third voltage to a channel of each of the one or more NAND memory cell strings,

wherein the second and third voltages are each different from the first voltage and the second voltage is selected based on the position of the first word line in each of the one or more NAND memory cell strings.

33. A method of programming memory cells in a NAND architecture array of non-volatile memory cells, comprising:

applying a first voltage to a first word line of a block, each first word line coupled to a selected non-volatile memory cell of one or more NAND memory cell strings of the block;

applying a second voltage to one or more second word lines of the block, each second word line coupled to one or more unselected non-volatile memory cells of the one or more NAND memory cell strings of the block; and

applying a third voltage to a channel of each of the one or more NAND memory cell strings;

wherein the second and third voltages are each different from the first voltage and the second voltage is selected by the position of the first word line in each of the one or more NAND memory cell strings;

wherein the first and third voltages are expected to cause programming of a nominal memory cell of each of the one or more NAND memory cell strings of the block if applied across its word line and the channel.

34. The method of claim 33, wherein the first voltage is greater than the second and third voltages.

35. The method of claim 34, wherein the second voltage is greater than the third voltage.

36. The method of claim 33, further comprising:

applying a fourth voltage to one or more third word lines of the block, each third word line coupled to one or more of the non-volatile memory cells of the one or more NAND memory cell strings of the block;

wherein the fourth voltage is different from at least the first and second voltages.

37. A method of programming memory cells of a NAND architecture memory string, comprising:

applying a programming voltage to a first memory cell of a NAND architecture memory string and applying a lower pass voltage to a gate of one or more unselected memory cells of the string;

applying a programming voltage to a middle memory cell of a NAND architecture memory string and applying an average pass voltage to a gate of one or more unselected memory cells of the string; and

applying a programming voltage to a last memory cell of a NAND architecture memory string and applying a higher pass voltage to a gate of one or more unselected memory cells of the string.

38. The method of claim 37, wherein applying a programming voltage to a middle memory cell of a NAND architecture memory string and applying an average pass voltage to a gate of one or more unselected memory cells of the string and applying a programming voltage to a last memory cell of a NAND architecture memory string and applying a higher pass voltage to a gate of one or more unselected memory cells of the string further comprises applying a very low pass voltage to a gate of the first memory cell of the string, wherein the first memory cell is coupled to a WL0 word line that is located adjacent to a source side select gate.

39. The method of claim 38, wherein applying a very low pass voltage to a gate of the first memory cell of the string further comprises applying a very low pass voltage that is less than the lower pass voltage and greater than a maximum threshold voltage level of a programmed non-volatile memory cell.

40. The method of claim 37, wherein applying a programming voltage to a first, middle, and last memory cell of a NAND architecture memory string further comprises applying one of a channel program voltage and a channel inhibit-program voltage to a channel of the string.

41. A method of programming memory cells of a NAND architecture memory string, comprising:

applying a programming voltage to a first memory cell of a NAND architecture memory string and applying a lower pass voltage to a gate of one or more unselected memory cells of the string;

applying a programming voltage to a middle memory cell of a NAND architecture memory string, applying an average pass voltage to a gate of one or more unselected memory cells of the string, and applying a very low pass voltage to a gate of the first memory cell of the string, wherein the first memory cell is coupled to a word line that is located adjacent to a source side select gate; and

applying a programming voltage to a last memory cell of a NAND architecture memory string, applying a higher pass voltage to a gate of one or more unselected memory cells of the string, and applying a very low pass voltage to a gate of the first memory cell of the string, wherein the first memory cell is coupled to the word line that is located adjacent to a source side select gate.

42. The method of claim 41, wherein applying a much lower than the average pass voltage to a gate of the first memory cell of the string further comprises applying a pass voltage that is much lower than the lower pass voltage but is greater than a maximum threshold voltage level of a nominal programmed non-volatile memory cell.

43. The method of claim 41, wherein applying a programming voltage to a first, middle, and last memory cell of a NAND architecture memory string further comprises applying one of a channel program voltage and a channel inhibit-program voltage to a channel of the string.

44. A method of operating a NAND architecture non-volatile memory array, comprising:

selecting a memory cell in one or more NAND architecture memory cell strings for programming in a selected block of non-volatile memory cells, where the selected memory cell in each of the one or more memory cell strings is coupled to a word line;

applying a program voltage to the word line coupled to the selected memory cells; and

selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings based on the position of the selected memory cells and word line in the one or more NAND architecture memory strings, wherein a second pass voltage is applied to a first memory cell of the one of more NAND architecture memory cells if the first memory cell is not currently selected for programming, where the first memory cell is coupled to a WL0 word line that is located adjacent to a source side select gate.

45. The method of claim 44, wherein applying second pass voltage to a first memory cell of the one of more NAND architecture memory cells if the first memory cell is not currently selected for programming further comprises applying a pass voltage that is lower than the average pass voltage but is greater than a maximum threshold voltage level of a programmed non-volatile memory cell.

46. The method of claim 44, wherein selecting and applying a pass voltage to one or more unselected word lines coupled to one or more unselected memory cells of the one or more memory cell strings based on the position of the selected memory cells and word line in the one or more NAND architecture memory strings further comprises selecting and applying a lower than average pass voltage to the one or more unselected word lines when an initial word line in the one or more NAND architecture memory strings is the selected word line and selecting and applying a higher than average pass voltage to the one or more unselected word lines when a final word line in the one or more NAND architecture memory strings is the selected word line.

47. A method of programming two or more memory cells of a NAND architecture memory string, comprising:

selecting a memory cell of a NAND architecture memory string of a non-volatile memory array to be programmed; and

selecting and applying a pass voltage to a gate of one or more unselected memory cells of the string based on a sequence of programming the two or more memory cells in the NAND architecture memory string.

48. The method of claim 47, wherein selecting and applying a pass voltage to a gate of one or more unselected memory cells of the string based on a sequence of programming the two or more memory cells in the NAND architecture memory string further comprises selecting and applying a lower than average pass voltage to a gate of one or more unselected memory cells of the string when an initial memory cell in the NAND architecture memory string is programmed and selecting and applying a higher than average pass voltage to a gate of one or more unselected memory cells of the string when a final memory cell in the NAND architecture memory string is programmed.

49. The method of claim 47, wherein selecting and applying a pass voltage to a gate of one or more unselected memory cells of the string based on a sequence of programming the two or more memory cells in the NAND architecture memory string further comprises selecting and applying a pass voltage to a gate of one or more unselected memory cells of the string based on a number of previously programmed memory cells of the selected memory cell in the NAND architecture memory string and the probability of program disturb in an erase block containing the NAND architecture memory string for the selected pass voltage and selected memory cell position being programmed.

50. The method of claim 47, wherein selecting and applying a pass voltage to a gate of one or more unselected memory cells of the string based on a sequence of programming the two or more memory cells in the NAND architecture memory string further comprises selecting and applying two or more pass voltages to different gates of the one or more unselected memory cells of the string.

51. The method of claim 47, further comprising selecting a second pass voltage to apply to one or more second unselected memory cells of the string based on one of a physical or electrical characteristic of the one or more second unselected memory cells, and the position of the one or more second unselected memory cells in the NAND architecture memory string.