Synchronous memory device

• US 20070047340A1
• Filed: 08/29/2006
• Published: 03/01/2007
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Youn-cheul
• Granted Patent: US 7,554,878 B2
• Time in Patent Office: Days
• US Class Current: 365/194
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal.

Claims

1. A synchronous memory device comprising:

a read command buffer providing a read signal in response to a read command;

a replica circuit providing a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes the read command buffer to provide the read signal; and

a latency circuit receiving the read signal, and providing a latency signal having a predetermined time difference corresponding to a column access strobe (CAS) latency with respect to the read signal in response to the transfer signal.

2. The synchronous memory device as set forth in claim 1, wherein the latency circuit includes a plurality of flip-flop circuits connected in series, and wherein a first flip-flop circuit of the plurality of flip-flop circuits that receives the read signal operates in response to the transfer signal.

3. The synchronous memory device as set forth in claim 2, wherein the latency circuit includes a plurality of switches which are connected to input and/or output terminals of the plurality of flip-flop circuits, respectively, and are turned on in response to the CAS latency signal.

4. A synchronous memory device, comprising:

a clock recovery circuit generating a data output clock signal in response to an external clock signal and a feedback clock signal;

a first replica circuit receiving the data output clock signal, providing a plurality of first transfer signals whose time differences with respect to the data output clock signal are shorter than a period that it takes a data output buffer to output data received from a memory cell array, and providing a feedback dock signal whose time difference with respect to the data output clock signal is substantially identical to a period that it takes the data output buffer to output data received from the memory cell array;

a second replica circuit receiving the feedback clock signal and providing a second transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that a it takes a read command buffer to provide a read signal; and

a latency circuit receiving the read signal, and providing latency signals in response to the second transfer signal and the plurality of first transfer signals.

5. The synchronous memory device as set forth in claim 4, wherein the first replica circuit includes a plurality of delay circuits, and wherein the respective first transfer signals are provided through different numbers of delay circuits.

6. The synchronous memory device as set forth in claim 4, wherein the latency circuit receives a column access strobe (CAS) latency signal, and provides a latency signal at a timing corresponding to the CAS latency signal.

7. The synchronous memory device as set forth in claim 4, wherein the latency circuit includes a plurality of flip-flop circuits connected in series, and wherein each of the plurality of flip-flop circuits operates in response to the second transfer signal or first transfer signal.

8. The synchronous memory device as set forth in claim 7, wherein the latency circuit includes a plurality of switches which are connected to input and/or output terminals of the plurality of flip-flop circuits, respectively, and are turned on in response to a CAS latency signal.

9. A synchronous memory device comprising:

a clock recovery circuit generating a data output clock signal in response to an external clock signal and a feedback clock signal;

a first replica circuit receiving the data output clock signal and providing a feedback clock signal whose time difference with respect to the data output clock signal is substantially identical to a period that it takes a data output buffer to output data received from a memory cell array;

a clock delay circuit receiving the data output clock signal and providing first transfer signals having predetermined time differences with respect to the data output clock signal;

a second replica circuit receiving the feedback clock signal and providing a second transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide a read signal; and

a latency circuit receiving the read signal and providing latency signals in response to the second transfer signal and the first transfer signals.

10. The synchronous memory device as set forth in claim 9, wherein the latency circuit receives a column access strobe (CAS) latency signal, and provides a latency signal at a timing corresponding to the CAS latency signals.

11. The synchronous memory device as set forth in claim 9, wherein the latency circuit includes a plurality of flip-flop circuits connected in series, and each of the plurality of flip-flop circuits operates in response to the second transfer signal or the first transfer signal.

12. The synchronous memory device as set forth in claim 11, wherein the latency circuit includes a plurality of switches which are connected to input and/or output terminals of the plurality of flip-flop circuits, respectively, and are turned on in response to the CAS latency signal.