Two-step channel selection for wireless receiver and transmitter front-ends

• US 20070047669A1
• Filed: 08/26/2005
• Published: 03/01/2007
• Est. Priority Date: 08/26/2005
• Status: Active Grant

• Current Assignee: University of Macau
• Original Assignee: University of Macau
• Inventors: Mak, Pui-In, U, Seng-Pan, Martins, Rui Paulo da Silva
• Granted Patent: US 7,529,322 B2
• Time in Patent Office: Days
• US Class Current: 375/316
• CPC Class Codes: H03D 3/007 by converting the oscillations into two quadrature related signals H03D3/245 takes precedence
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes

Abstract

A reconfigurable receiver, a reconfigurable transmitter and a multimode receiver are disclosed, operating in accordance with a two-step channel selection. In the receiver, the first step provides for a coarse radio frequency (RF) channel selection, to downconvert a desired channel and an image channel of the desired channel to IF. The second step provides for a fine intermediate frequency (IF) channel selection to select either the desired channel or the image channel. In the transmitter, the first step provides for a fine channel selection and upconversion of a desired channel to either positive or negative IF. The second step is a coarse channel selection and upconversion of a desired channel to the RF. The receiver and transmitter can be used in a transceiver.

Claims

1. A two-step channel selection apparatus comprising:

a radio frequency to intermediate frequency (IF) downconverter comprising a local oscillator; and

a frequency synthesizer associated with the local oscillator to select a first desired channel and a second desired channel, the first and second desired channels being an image of each other, wherein the frequency synthesizer has a step size larger than one channel spacing.

2. The apparatus of claim 1, wherein the frequency of a desired channel (f_desired), the frequency of an image of the desired channel (f_image) and IF are related so that

|f_desired-f_image|=2IF.

3. The apparatus of claim 1, wherein the frequency synthesizer has a number of locking positions inferior to a total number of channels being selected.

4. The apparatus of claim 1, wherein the local oscillator is provided with 0°

and 90°

phase shifts, to allow downconversion of a plurality of channels in two parallel paths having a 90°

phase difference.

5. The apparatus of claim 1, further comprising a channel selection filter, the channel selection filter either selecting the first desired channel at a positive intermediate frequency or selecting the first desired channel at a negative intermediate frequency.

6. The apparatus of claim 1, wherein IF=(n+0.5) CS, CS being the channel spacing, n=0, 1, 2,3 . . .

7. The apparatus of claim 1, further comprising a second local oscillator and an intermediate frequency to baseband downconverter to perform intermediate frequency to baseband downconversion of the selected channel.

8. The apparatus of claim 2, further comprising a second local oscillator and an intermediate frequency to baseband downconverter to perform intermediate frequency to baseband downconversion of the selected channel.

9. The apparatus of claim 1, wherein said downconversion is controllable between an upper sideband intermediate frequency and a lower sideband intermediate frequency.

10. A reconfigurable receiver capable of operating at a zero intermediate frequency (zero-IF) mode or a low intermediate frequency (low-IF) mode, the receiver comprising:

a radio frequency to intermediate frequency downconverter and a first local oscillator to perform radio frequency to intermediate frequency downconversion; and

a frequency synthesizer associated with the first local oscillator, to select a channel in the zero-IF mode and a plurality of channels in the low-IF mode, said plurality of channels comprising a first desired channel and a second desired channel, the first and second desired channels being an image of each other, wherein the frequency synthesizer has a step size larger than one channel spacing.

11. The receiver of claim 10, wherein the frequency of a desired channel (f_desired), the frequency of an image of the first desired channel (f_image) and IF are related so that

|f_desired-f_image|=2IF.

12. The receiver of claim 10, wherein the frequency synthesizer has a number of locking positions inferior to a total number of available channels.

13. The receiver of claim 10, wherein the first local oscillator is provided with 0°

and 90°

phase shifts, to allow downconversion of the plurality of channels in two parallel paths having a 90°

phase difference.

14. The receiver of claim 10, further comprising a second local oscillator and an intermediate frequency to baseband downconverter to perform intermediate frequency to baseband downconversion of the first desired channel or the second desired channel wherein, in the low IF-mode said downconversion is controllable between an upper sideband intermediate frequency and a lower sideband intermediate frequency and, in the zero-IF mode, said downconversion is not performed.

15. The receiver of claim 10, further comprising a channel selection filter, the channel selection filter having a first mode where the first desired channel is selected at a positive intermediate frequency in the low-IF mode, a second mode where the second desired channel is selected at a negative intermediate frequency in the low-IF mode, and a third mode where the first desired channel is selected at baseband in the zero-IF mode.

16. The receiver of claim 14, wherein the second local oscillator is provided with 0°

, 90°

, 180° and

270°

phase shifts, to allow selection either of the first desired channel or the second desired channel.

17. The receiver of claim 10, wherein, in the low-IF mode, IF=(n+0.5)CS, CS being the channel spacing, n=0, 1, 2, 3 . . .

18. The receiver of claim 14, further comprising an analog-to-digital converter located downstream of the second oscillator.

19. The receiver of claim 10, further comprising a decimation filter.

20. The receiver of claim 14, wherein the intermediate frequency to baseband downconverter is a double-quadrature sampling-mixer arrangement, the sampling frequency of the sampling-mixer arrangement being four times the intermediate frequency.

21. The receiver of claim 14, wherein the second local oscillator is a digital clock generator comprising D flip-flops and a non-overlap clock generator, and wherein channel selection is performed inside the digital clock generator.

22. The receiver of claim 14, wherein the frequency synthesizer comprises an integer-N phase-locked loop (PLL) and frequency dividers for channel selection.

23. A reconfigurable transmitter capable of operating in a direct-up mode or a two-step-up mode, wherein in the direct-up mode the intermediate frequency IF=0, the transmitter comprising:

a baseband to intermediate frequency upconverter to perform baseband to intermediate frequency upconversion of a signal to either a positive IF or negative IF in the two-step-up mode, the upconverter being-bypassed in the direct-up mode;

an intermediate frequency to radio frequency upconverter and a local oscillator to perform intermediate frequency to radio frequency upconversion; and

a frequency synthesizer having a step size larger than one channel spacing.

24. The transmitter of claim 23, wherein the frequency synthesizer has a number of locking positions inferior to a total number of channels that are being upconverted.

25. The transmitter of claim 23, wherein the local oscillator is provided with 0°

and 90°

phase shifts, to allow downconversion of the plurality of channels in two parallel paths having a 90°

phase difference.

26. The transmitter of claim 23, further comprising a channel selection filter, the channel selection filter having a first mode wherein a desired channel is selected at a positive intermediate frequency in the two-step-up mode, a second mode where the desired channel is selected at a negative intermediate frequency in the two-step-up mode, and a third mode where the desired channel is selected at baseband in the direct-up mode.

27. The transmitter of claim 23, wherein the local oscillator is provided with 0°

, 90°

, 180° and

270°

phase shifts, to allow upconversion of a desired channel to positive or negative intermediate frequency.

28. The transmitter of claim 23, further comprising an analog-to-digital converter located downstream of the oscillator.

29. The transmitter of claim 23 wherein, in the two-step-up mode, IF=(n+0.5)CS, CS being the channel spacing, n=0, 1, 2, 3 . . .

30. The transmitter of claim 23, wherein the local oscillator is a digital clock generator, and wherein channel selection is performed inside the digital clock generator.

31. The transmitter of claim 23, further comprising an analog-to-digital converter located upstream of the oscillator.

32. The transmitter of claim 23, wherein the baseband to intermediate frequency upconverter is a double-quadrature sampling-mixer arrangement.

33. The transmitter of claim 23, wherein the frequency synthesizer comprises an integer-N phase locked loop (PLL) and frequency dividers for channel selection.

34. A multimode receiver capable of operating at multiple intermediate frequencies, comprising:

a radio frequency to intermediate frequency downconverter and a first local oscillator to perform radio frequency to intermediate frequency (IF) downconversion;

a frequency synthesizer associated with the first local oscillator, to select a plurality of channels in a first frequency mode, said plurality of channels comprising a first desired channel and a second desired channel, the first and second desired channels being an image of each other, wherein the frequency synthesizer has a step size larger than one channel spacing; and

a second local oscillator and an intermediate frequency to baseband downconverter to perform intermediate frequency to baseband downconversion of the first desired channel or the second desired channel, wherein the downconverter is controllable in the first frequency mode and adapted to be bypassed in a second frequency mode.

35. The receiver of claim 34, wherein the frequency of a desired channel (f_desired), the frequency of an image of the desired channel (f_image) and IF are related so that

|f_desired-f_image|=2IF.

36. The receiver of claim 35, wherein the frequency synthesizer has a number of locking positions inferior to a total number of available channels.

37. The receiver of claim 36, wherein the first frequency mode is a low-intermediate frequency mode with IF=(n+0.5)CS, CS being the channel spacing, n=0, 1, 2, 3 . . . and the second frequency mode is a zero-intermediate frequency mode with IF=0.

38. The receiver of claim 36, wherein the first local oscillator is provided with 0°

and 90°

phase shifts, to allow downconversion of the plurality of channels in two parallel paths having a 90°

phase difference.

39. The receiver of claim 36, further comprising a pre-filter located upstream of the intermediate frequency to baseband downconverter, the pre-filter configurable to operate either in the first frequency mode or the second frequency mode.

40. The receiver of claim 36, further comprising a programmable gain amplifier, the amplifier being operated both in the first frequency mode and the second frequency mode.

41. The receiver of claim 39, further comprising a programmable gain amplifier, the amplifier being operated both in the first frequency mode and the second frequency mode.

42. The receiver of claim 36, wherein the intermediate frequency to baseband downconverter comprises a mixed-signal clock generator.