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Clock and data recovery circuit having wide phase margin

  • US 20070047683A1
  • Filed: 08/23/2006
  • Published: 03/01/2007
  • Est. Priority Date: 08/24/2005
  • Status: Active Grant
First Claim
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1. A clock and data recovery (CDR) circuit comprising:

  • a sampler configured to sample serial data in response to a recovery clock signal to generate a serial sampling pulse;

    a CDR loop configured to transform the serial sampling pulse into parallel data, configured to generate a plurality of phase signals with a first speed based on the parallel data, and configured to generate a phase control signal with a second speed higher than the first speed based on the plurality of phase signals; and

    a phase interpolator configured to generate the recovery clock signal fed to the sampler by controlling a phase of a reference clock signal in response to the phase control signal from the CDR loop.

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