Clock and data recovery circuit having wide phase margin

• US 20070047683A1
• Filed: 08/23/2006
• Published: 03/01/2007
• Est. Priority Date: 08/24/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Okamura, Hitoshi, Shin, Min-Bo
• Granted Patent: US 7,961,830 B2
• Time in Patent Office: Days
• US Class Current: 375/355
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0079 Receiver details
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A clock and data recovery (CDR) circuit includes a sampler, a CDR loop and a phase interpolator. The sampler samples serial data in response to a recovery clock signal to generate a serial sampling pulse. The CDR loop transforms the serial sampling pulse into parallel data, generates a plurality of phase signals with a first speed based on the parallel data, and generates a phase control signal with a second speed higher than the first speed based on the plurality of phase signals. The phase interpolator generates the recovery clock signal by controlling a phase of a reference clock signal in response to the phase control signal. Therefore, the CDR circuit may recover data and a clock with a relatively high speed.

Claims

1. A clock and data recovery (CDR) circuit comprising:

a sampler configured to sample serial data in response to a recovery clock signal to generate a serial sampling pulse;

a CDR loop configured to transform the serial sampling pulse into parallel data, configured to generate a plurality of phase signals with a first speed based on the parallel data, and configured to generate a phase control signal with a second speed higher than the first speed based on the plurality of phase signals; and

a phase interpolator configured to generate the recovery clock signal fed to the sampler by controlling a phase of a reference clock signal in response to the phase control signal from the CDR loop.

2. The CDR circuit of claim 1, wherein the CDR loop is configured to transform the serial sampling pulse into the parallel data of n bits, configured to generate the plurality of phase signals with the first speed based on a plurality of data groups in response to a clock signal having a 1/n frequency relative to the recovery clock signal, and configured to generate the phase control signal with the second speed based on the plurality of phase signals, the parallel data of n bits being divided into the plurality of data groups.

3. The CDR circuit of claim 2, wherein the recovery clock signal includes four recovery clock signals having phase differences of substantially 90°

between each other.

4. The CDR circuit of claim 3, wherein the n-bit parallel data includes:

first parallel data transformed from the serial sampling pulse that is sampled by the recovery clock signals corresponding to phases 0° and

180°

; and

second parallel data transformed from the serial sampling pulse that is sampled by the recovery clock signals corresponding to phases 90° and

270°

.

5. The CDR circuit of claim 1, wherein the CDR loop comprises:

a deserializer configured to transform the serial sampling pulse into the parallel data of n bits in response to the recovery clock signal;

a phase detection logic configured to generate k first phase signals from k data groups in response to the recovery clock signal, the parallel data of n bits being divided by m bits into the k data groups;

a selector configured to sum the k first phase signals sequentially with a predetermined phase interval to generate a second phase signal; and

a phase interpolation controller configured to generate the phase control signal based on the second phase signal.

6. The CDR circuit of claim 5, wherein n is 20, m is 5, and k is 4.

7. The CDR circuit of claim 5, wherein n is 40, m is 5, and k is 8.

8. The CDR circuit of claim 5, wherein the k data groups are partially superimposed such that a predetermined number of bits of the respective data group are commonly included in the next data group.

9. The CDR circuit of claim 8, wherein n is 20, m is 10, the number of the common bits included in the two data groups is 5, and k is 4.

10. The CDR circuit of claim 8, wherein n is 40, m is 10, the number of the common bits included in the two data groups is 5, and k is 8.

11. The CDR circuit of claim 1, wherein the CDR loop comprises:

a deserializer configured to transform the serial sampling pulse into the parallel data of n bits in response to the recovery clock signal;

a phase detection logic configured to generate k first phase signals from k data groups in response to the recovery clock signal, the parallel data of n bits being divided by m bits into the k data groups;

a loop filter configured to filter the k first phase signals to generate k second phase signals;

a selector configured to sum the k second phase signals sequentially with a predetermined phase interval to generate a third phase signal; and

a phase interpolation controller configured to generate the phase control signal based on the third phase signal.

12. The CDR circuit of claim 11, wherein n is 20, m is 5, and k is 4.

13. The CDR circuit of claim 11, wherein n is 40, m is 5, and k is 8.

14. The CDR circuit of claim 11, wherein the k data groups are partially superimposed such that a predetermined number of bits of the respective data group are commonly included in the next data group.

15. The CDR circuit of claim 14, wherein n is 20, m is 10, the number of the common bits included in the two data groups is 5, and k is 4.

16. The CDR circuit of claim 14, wherein n is 40, m is 10, the number of the common bits included in the two data groups is 5, and k is 8.

17. A method of recovering a clock and data, the method comprising:

sampling serial data in response to a recovery clock signal to generate a serial sampling pulse;

transforming the serial sampling pulse into parallel data;

generating a plurality of phase signals with a first speed based on the parallel data;

generating a phase control signal with a second speed higher than the first speed based on the plurality of phase signals; and

generating the recovery clock signal by controlling a phase of a reference clock signal in response to the phase control signal, the reference signal being externally provided.

18. The method of claim 17, wherein the parallel data is n-bit parallel data, and generating the plurality of phase signals with the first speed comprises generating the plurality of phase signals with the first speed based on a plurality of data groups in response to a clock signal having a 1/n frequency relative to the recovery clock signal, the n-bit parallel data being divided into the data groups.

19. The method of claim 18, wherein the recovery clock signal includes four recovery clock signals having phase differences of substantially 90°

between each other.

20. The method of claim 19, wherein the n-bit parallel data includes:

first parallel data transformed from the serial sampling pulse that is sampled by the recovery clock signals corresponding to phases 0° and

180°

; and

second parallel data transformed from the serial sampling pulse that is sampled by the recovery clock signals corresponding to phases 900 and 2700.

21. The method of claim 17, wherein the parallel data is n-bit parallel data, and generating the plurality of phase signals comprises:

generating k first phase signals from k data-groups in response to the recovery clock signal, the n-bit parallel data being divided by m bits into the k data groups;

summing the k first phase signals sequentially with a predetermined phase interval to generate a second phase signal; and

generating the phase control signal based on the second phase signal.

22. The method of claim 21, wherein n is 20, m is 5, and k is 4.

23. The method of claim 21, wherein n is 40, m is 5, and k is 8.

24. The method of claim 21, wherein the k data groups are partially superimposed such that a predetermined number of bits of the respective data group are commonly included in the next data group.

25. The method of claim 24, wherein n is 20, m is 10, the number of the common bits included in the two data groups is 5, and k is 4.

26. The method of claim 24, wherein n is 40, m is 10, the number of the common bits included in the two data groups is 5, and k is 8.

27. The method of claim 17, wherein the parallel data is n-bit parallel data, and generating the plurality of phase signals comprises:

generating k first phase signals from k data groups in response to the recovery clock signal, the n-bit parallel data being divided by m bits into the k data groups;

filtering the k first phase signals to generate k second phase signals;

summing the k second phase signals sequentially with a predetermined phase interval to generate a third phase signal; and

generating the phase control signal based on the third phase signal.

28. The method of claim 27, wherein n is 20, m is 5, and k is 4.

29. The method of claim 27, wherein n is 40, m is 5, and k is 8.

30. The method of claim 25, wherein the k data groups are partially superimposed such that a predetermined number of bits of the respective data group are commonly included in the next data group.

31. The method of claim 30, wherein n is 20, m is 10, the number of the common bits included in the two data groups is 5 and k is 4.

32. The method of claim 30, wherein n is 40, m is 10, the number of the common bits included in the two data groups is 5 and k is 8.