Stackable splice chip device
First Claim
Patent Images
1. A splice chip arrangement that mounts to a splice tray, the splice chip arrangement comprising:
- a) a first splice chip and a second splice chip secured to one another in a stacked relationship, each of the first and second splice chips including;
i) a base having a first end and a second opposite end; and
ii) a plurality of channels sized to receive splice elements;
b) wherein the first end of the first splice chip is pivotally interconnected to the second end of the second splice chip; and
wherein the second end of the first splice chip is snap-fit to the first end of the second splice chip.
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Accused Products
Abstract
A splice tray arrangement including a tray and a splice chip arrangement. The splice chip arrangement including stackable splice chips defining channels for holding splice elements. Each of the splice chips including a mounting arrangement for mounting the splice chip at a mounting location on the tray, and a stacking arrangement for mounting the splice chip upon another splice chip.
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Citations
29 Claims
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1. A splice chip arrangement that mounts to a splice tray, the splice chip arrangement comprising:
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a) a first splice chip and a second splice chip secured to one another in a stacked relationship, each of the first and second splice chips including;
i) a base having a first end and a second opposite end; and
ii) a plurality of channels sized to receive splice elements;
b) wherein the first end of the first splice chip is pivotally interconnected to the second end of the second splice chip; and
wherein the second end of the first splice chip is snap-fit to the first end of the second splice chip. - View Dependent Claims (3, 4, 5, 6, 8, 9, 10, 11)
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2. (canceled)
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7. (canceled)
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12. A splice tray arrangement, comprising:
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a) a tray having a splice chip mounting location;
b) a first splice chip positioned at the mounting location, the first splice chip including a plurality of splice holding structures, the first splice chip including mounting structure configured such that the first splice chip laterally slides into position at the mounting location; and
c) a second splice chip disposed on the first splice chip at the mounting location, the second splice chip including a plurality of splice holding structures. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A method of assembling a splice tray arrangement, the method comprising the steps of:
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a) securing a first splice chip to a tray at a mounting location by sliding the first splice chip in a lateral direction along a mounting surface of the tray; and
b) securing a second splice chip to the first splice chip at the mounting location. - View Dependent Claims (21, 22, 23)
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20. (canceled)
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24. A splice chip, comprising:
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a) a base having first and second opposite ends;
b) a plurality of channels sized to receive splice elements; and
c) a stacking arrangement, the stacking arrangement including;
i) mounting guides located at the opposite ends of the base, the mounting guides being configured to selectively mount the splice chip to another splice chip in a stacked relationship, the mounting guides further being configured to selectively mount the splice chip to a splice tray;
ii) latch members located at the opposite ends of the base, the latch members being configured to selectively receive another splice chip in a stacked relationship;
iii) alignment structure formed in a bottom surface of the base that aligns the splice chip relative to another splice chip when the splice chip is selectively mounted to another splice chip in a stacked relationship; and
iv) corresponding alignment structure located adjacent to the channels that aligns another splice chip relative to the splice chip when the splice chip selectively receives another splice chip in a stacked relationship. - View Dependent Claims (25, 26, 27, 28)
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29. A splice chip, comprising:
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a) a base having first and second opposite ends;
b) a plurality of channels sized to receive splice elements; and
c) a stacking arrangement, the stacking arrangement including;
i) mounting guides located at the opposite ends of the base, the mounting guides being configured to selectively mount the splice chip to another splice chip in a stacked relationship, the mounting guides further being configured to selectively mount the splice chip to a splice tray;
ii) latch members located at the opposite ends of the base, the latch members being configured to selectively receive another splice chip in a stacked relationship;
iii) a recess formed in a bottom surface of the base; and
iv) a guide structure located adjacent to the channels;
v) wherein one of the recess and guide structure prevents lateral movement of the splice chip when the splice chip is selectively mounted to another spice chip in a stacked relationship.
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Specification