Wafer-level package and IC module assembly method for the wafer-level package

• US 20070048901A1
• Filed: 08/30/2005
• Published: 03/01/2007
• Est. Priority Date: 08/30/2005
• Status: Active Grant

• Current Assignee: Mutual-Pak Technology Co., Ltd.
• Original Assignee: Mutual-Pak Technology Co., Ltd.
• Inventors: Hwan, Lu-Chen
• Granted Patent: US 7,273,768 B2
• Time in Patent Office: Days
• US Class Current: 438/108
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/11505 Sintering
• CPC Class Codes: H01L 2224/1184 involving a mechanical process, e.g. planarising the bump connector
• CPC Class Codes: H01L 2224/11848 Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/2784 involving a mechanical process, e.g. planarising the layer connector
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A wafer-level package and an IC module assembly method for a wafer-level package are provided in the present invention. The method comprises forming a metal bump on a wafer, applying a high polymer resin coating to the wafer, grinding a surface of the resin coating, printing an endpoint on the wafer, a grinding and cutting step and bonding the chips to an antenna or substrate with SMT. The present invention can be used to manufacture high quality chips of low cost with mass production to significantly reduce cost and maintain high quality of the products.

Claims

1. A wafer-level package and an IC module assembly method for the wafer-level package comprising:

forming a metal bump on a wafer;

printing a conductive metal paste on an I/O pad of the wafer with a steel plate printing technique, then solidifying to form the metal bump;

applying a high polymer resin coating;

applying the high polymer resin coating to the surface of the wafer over the metal bump with a printing technique and solidifying the resin coating;

grinding a surface of the resin coating;

grinding the solidified resin coating on the surface of the wafer until the metal bump is exposed and a required thickness of the resin coating is reached;

printing an endpoint on the exposed metal bump;

an endpoint referring to a joint point of a wafer die part and an antenna or a substrate;

grinding and cutting;

grinding a back side of the wafer to a required thickness, then cutting the wafer into multiple chips to complete a package process; and

bonding the chips to an antenna or substrate with SMT (surface mounting technology).

2. The wafer-level package and the IC module assembly method for the wafer-level package as claimed in claim 1, wherein the conductive metal paste is a cooper paste.

3. The wafer-level package and the IC module assembly method for the wafer-level package as claimed in claim 1, wherein the conductive metal paste is a silver paste.

4. The wafer-level package and the IC module assembly method for the wafer-level package as claimed in claim 1, wherein the conductive metal paste is a solder paste.

5. The wafer-level package and the IC module assembly method for the wafer-level package as claimed in claim 1, wherein the endpoint is a silver paste.

6. The wafer-level package and the IC module assembly method for the wafer-level package as claimed in claim 1, wherein the endpoint is a solder paste.