Transistor gate forming methods and transistor structures
First Claim
1. A transistor gate forming method comprising:
- forming a gate metal layer within a gate line opening extending into a semiconductive substrate; and
forming a gate fill layer within the opening over the metal layer, the fill layer being substantially selectively etchable with respect to the metal layer.
8 Assignments
0 Petitions
Accused Products
Abstract
A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
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Citations
54 Claims
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1. A transistor gate forming method comprising:
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forming a gate metal layer within a gate line opening extending into a semiconductive substrate; and
forming a gate fill layer within the opening over the metal layer, the fill layer being substantially selectively etchable with respect to the metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A transistor gate forming method comprising:
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forming a gate metal layer containing titanium nitride within a gate line opening extending into a semiconductive substrate; and
filling all of the opening over the metal layer with a gate fill layer containing polysilicon, a thickness of the fill layer within the opening being greater than a thickness of the metal layer, the fill layer being substantially selectively etchable with respect to the metal layer, the metal layer being substantially selectively etchable with respect to the fill layer, the fill layer exhibiting a porosity greater than a porosity of the metal layer, and the metal layer/fill layer combination exhibiting less intrinsic stress than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer.
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17. (canceled)
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18. (canceled)
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19. A transistor gate forming method comprising:
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forming a gate line opening extending into a semiconductive substrate, the opening having a semiconductive bottom and semiconductive side walls;
forming a gate dielectric layer within the opening over the semiconductive side walls and semiconductive bottom, the dielectric layer having an insulative bottom and insulative side walls;
forming a gate metal layer within the opening over the insulative bottom and insulative side walls, the metal layer having a conductive bottom and conductive side walls;
forming a gate fill layer within the opening over the conductive bottom and conductive side walls; and
removing excess fill layer substantially selectively with respect to the metal layer while exposing a portion of the metal layer under the fill layer without exposing the dielectric layer under the metal layer.
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20-35. -35. (canceled)
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36. A transistor gate forming method comprising:
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forming a gate line opening extending into a semiconductive substrate, the opening having a semiconductive bottom and semiconductive side walls;
forming a gate dielectric layer within the opening over the semiconductive side walls and semiconductive bottom, the dielectric layer having an insulative bottom and insulative side walls;
forming a gate metal layer containing titanium nitride within the opening over the insulative bottom and insulative side walls, the metal layer having a conductive bottom and conductive side walls;
filling all of the opening over the conductive bottom and conductive side walls with a gate fill layer containing polysilicon, a thickness of the fill layer within the opening being greater than a thickness of the metal layer;
removing excess fill layer selectively with respect to the metal layer at a selectivity ratio of at least 5 to 1 while exposing a portion of the metal layer under the fill layer within the opening, but without exposing the dielectric layer under the metal layer within the opening; and
removing the exposed portion of the metal layer selectively with respect to the fill layer at a selectivity ratio of at least 5 to 1, the fill layer exhibiting a porosity greater than a porosity of the metal layer, and the metal layer/fill layer combination exhibiting less intrinsic stress than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer.
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37. (canceled)
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38. (canceled)
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39. A transistor structure comprising:
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a gate line opening extending into a semiconductive substrate, the opening having a semiconductive bottom and semiconductive side walls;
a gate dielectric layer within the opening over the semiconductive side walls and semiconductive bottom, the dielectric layer having an insulative bottom and insulative side walls;
a gate metal layer within the opening over the insulative bottom and insulative side walls, the metal layer having a conductive bottom and conductive side walls;
a gate fill layer within the opening over the conductive bottom and conductive side walls, the metal layer/fill layer combination exhibiting less intrinsic stress than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)
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52. A transistor structure comprising:
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a gate line opening extending into a semiconductive substrate, the opening having a semiconductive bottom and semiconductive side walls;
a gate dielectric layer within the opening over the semiconductive side walls and semiconductive bottom, the dielectric layer having an insulative bottom and insulative side walls;
a gate metal layer containing titanium nitride within the opening over the insulative bottom and insulative side walls, the metal layer having a conductive bottom and conductive side walls;
a gate fill layer containing polysilicon filling all of the opening over the conductive bottom and conductive side walls, a thickness of the fill layer within the opening being greater than a thickness of the metal layer, the fill layer exhibiting the property of being substantially selectively etchable with respect to the metal layer, the metal layer exhibiting the property of being substantially selectively etchable with respect to the fill layer, the fill layer exhibiting a porosity greater than a porosity of the metal layer, the metal layer/fill layer combination exhibiting less intrinsic stress than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer.
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53. (canceled)
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54. (canceled)
Specification