Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
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Abstract
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
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Citations
41 Claims
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1-23. -23. (canceled)
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24. A semiconductor structure containing a vertical transistor, comprising:
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a substrate, wherein at least a portion of the work surface of the substrate is formed of polysilicon;
a polysilicon pillar extending vertically from the polysilicon surface of the substrate, the pillar having a top end, a top portion, a central portion, and a bottom portion;
a first source/drain region defined in the top portion of the pillar;
a channel region defined in the central portion of the pillar;
a second source/drain region defined in the bottom portion of the pillar;
a dielectric layer surrounding the central portion of the pillar and being in alignment with the channel region of the transistor; and
a transistor gate surrounding the central portion of the pillar with the dielectric layer between the transistor gate and the pillar, the transistor gate being aligned with the channel region of the transistor. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31)
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32. A DRAM array, comprising:
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a substrate;
M polysilicon digit lines formed in the substrate, wherein M is a positive integer;
an M×
N array of vertical transistors formed on the plurality of digit lines, wherein N is a positive integer and N transistors are formed on each digit line and are aligned with the transistors formed on adjacent rows to define N columns of transistors, and wherein each transistor comprises;
a polysilicon pillar epitaxially grown from one of the polysilicon digit lines, the pillar having a top end, a top portion, a central portion, and a bottom portion, a first source/drain region defined in the top portion of the pillar, a transistor channel region defined in the central portion of the pillar, and a second source/drain region defined in the bottom portion of the pillar, a dielectric layer formed on and surrounding the central portion of the pillar in alignment with the transistor channel region, and a transistor gate surrounding the central portion of the pillar with the dielectric layer between the transistor gate and the pillar, the transistor gate being aligned with the channel region of the transistor;
N conductive paths formed of the same material as the transistor gates, wherein each conductive path connects the transistor gates along a respective column, and is formed as an extension of the transistor gates along the column; and
M×
N capacitors, wherein each capacitor is stacked on the top end of the pillar of a respective transistor. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39)
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40. A DRAM memory device, comprising:
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a memory cell array containing M×
N cells for storing data signals of memory information, wherein each memory cell comprises;
a substrate, M polysilicon digit lines formed in the substrate, wherein M is a positive integer, an M×
N array of vertical transistors formed on the plurality of digit lines, wherein N is a positive integer and N transistors are formed on each digit line and are aligned with the transistors formed on adjacent rows to define N columns of transistors, and wherein each transistor includesa polysilicon pillar epitaxially grown from one of the polysilicon digit lines, the pillar having a top end, a top portion, a central portion, and a bottom portion, a first source/drain region defined in the top portion of the pillar, a transistor channel region defined in the central portion of the pillar, and a second source/drain region defined in the bottom portion of the pillar, a dielectric layer formed on and surrounding the central portion of the pillar in alignment with the transistor channel region, and a transistor gate completely surrounding the central portion of the pillar with the dielectric layer between the transistor gate and the pillar, the transistor gate being aligned with the channel region of the transistor, N conductive paths formed of the same material as the transistor gates, wherein each conductive path connects the transistor gates along a respective column, and is formed as an extension of the transistor gates along the column, and M×
N capacitors, wherein each capacitor is stacked on the top end of the pillar of a respective transistor;
a row and column address buffer for receiving external address signals for selecting a memory cell;
a row decoder;
a column decoder, wherein the row decoder and the column decoder together designate the selected memory cell by decoding the address signals;
a sense refresh amplifier for amplifying and reading a signal stored in the designated memory cell;
a data-in buffer for inputting data;
a data-out buffer for outputting data; and
a clock generator for generating a clock signal.
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41. A computer system, comprising:
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a processor; and
at least one semiconductor memory device coupled to exchange data with the processor via at least one memory bus, each memory device comprising a memory cell array containing M×
N cells for storing data signals of memory information, wherein each memory cell comprisesa substrate, M polysilicon digit lines formed in the substrate, wherein M is a positive integer, an M×
N array of vertical transistors formed on the plurality of digit lines, wherein N is a positive integer and N transistors are formed on each digit line and are aligned with the transistors formed on adjacent rows to define N columns of transistors, and wherein each transistor includesa polysilicon pillar epitaxially grown from one of the polysilicon digit lines, the pillar having a top end, a top portion, a central portion, and a bottom portion, a first source/drain region defined in the top portion of the pillar, a transistor channel region defined in the central portion of the pillar, and a second source/drain region defined in the bottom portion of the pillar, a dielectric layer formed on and surrounding the central portion of the pillar in alignment with the transistor channel region, and a transistor gate completely surrounding the central portion of the pillar with the dielectric layer between the transistor gate and the pillar, the transistor gate being aligned with the channel region of the transistor, N conductive paths formed of the same material as the transistor gates, wherein each conductive path connects the transistor gates along a respective column, and is formed as an extension of the transistor gates along the column, and M×
N capacitors, wherein each capacitor is stacked on the top end of the pillar of a respective transistor;
a row and column address buffer for receiving external address signals for selecting a memory cell;
a row decoder;
a column decoder, wherein the row decoder and the column decoder together designate the selected memory cell by decoding the address signals;
a sense refresh amplifier for amplifying and reading a signal stored in the designated memory cell;
a data-in buffer for inputting data;
a data-out buffer for outputting data; and
a clock generator for generating a clock signal.
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Specification