METHOD TO MANUFACTURE LDMOS TRANSISTORS WITH IMPROVED THRESHOLD VOLTAGE CONTROL

• US 20070048952A1
• Filed: 10/24/2006
• Published: 03/01/2007
• Est. Priority Date: 11/25/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lin, John, Hu, Binghua, Bolkhovsky, Vladimir, Lee, Howard, Edwards, Henry
• Granted Patent: US 7,696,049 B2
• Time in Patent Office: Days
• US Class Current: 438/301
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A double diffused region (65), (75), (85) is formed in an epitaxial layer (20). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).

Claims

1. A method for forming a doped region in a semiconductor substrate, comprising:

providing a semiconductor;

forming a patterned photoresist layer comprising at least one opening on said semiconductor;

implanting a first species into said semiconductor through said opening;

performing a hard bake on said patterned photoresist layer; and

implanting a second species into said semiconductor through said opening.

2. The method of claim 1 wherein said semiconductor comprises an epitaxial layer.

3. The method of claim 1 wherein said hard bake comprises heating said patterned photoresist layer to temperatures between 75°

C. and 200°

C.

4. The method of claim 3 wherein said first dopant species comprises a light mass implant specie.

5. The method of claim 4 wherein said second dopant species comprises a heavy mass implant specie.

6. A method for forming a double diffused region, comprising:

providing a semiconductor;

forming a patterned photoresist layer over said semiconductor wherein said patterned photoresist layer comprises at least one opening;

implanting a boron species into a region of said semiconductor through said opening;

performing a hard bake process on said patterned photoresist layer;

implanting an arsenic species into said region of said semiconductor through said opening; and

performing at least one thermal annealing cycle on said semiconductor.

7. The method of claim 6 wherein said thermal annealing cycle occurs at temperatures between 800°

C. and 1200°

C.