SYNCHRONIZATION METHOD FOR A MULTI-PROCESSOR SYSTEM AND THE APPARATUS THEREOF

• US 20070050527A1
• Filed: 12/28/2005
• Published: 03/01/2007
• Est. Priority Date: 08/26/2005
• Status: Abandoned Application

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Tuan, Cheng-Ming
• Application Number:
  US11/306,447
• Publication Number:
  US 20070050527A1
• Time in Patent Office: Days
• US Class Current: 710/200
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A synchronous method for a multi-processor system and the apparatus thereof are provided. The method comprises the following steps. First, a request for acquiring a spinlock from a processor is received and then the status of the spinlock is returned to the processor. If the spinlock is in an unlock state, the spinlock is changed to a locked state. If the spinlock is already in the locked state, the clock signal to the processor is suspended so that the processor is suspended and the suspended processor is added to a queue. Then, when a request for releasing the spinlock is received from a processor, the spinlock is changed to the unlocked state. Finally, if there are other processors waiting in the queue, one of the processors is selected from the queue according to a predetermined policy and the clock signal of the selected processor is resumed.

Claims

1. A synchronous method for a multi-processor system, characterized by:

suspending the operation of a processor from the time after the failure of the processor to acquire a spinlock to the time before the processor successfully acquires the spinlock.

2. The synchronous method of claim 1, wherein the method further includes the following step:

suspending the clock signal to the processor so that the operation of the processor is suspended.

3. The synchronous method of claim 1, wherein the method further includes the following steps:

receiving a request for acquiring the spinlock from a processor and returning the status of the spinlock to the requesting processor;

if the spinlock is in an unlocked state, changing the spinlock state to a locked state;

if the spinlock is in a locked state, suspending the operation of the processor and adding the processor to a waiting queue;

receiving a request for releasing the spinlock from a processor and changing the spinlock state to a an unlocked state; and

if some processors are still waiting in the queue, selecting a processor from the queue according to a predetermined policy and resuming the operation of the selected processor.

4. The synchronous method of claim 3, wherein the predetermined policy is to resume the operation of the processor entering the queue first and waiting in line the longest.

5. The synchronous method of claim 3, wherein the predetermined policy is based on a predetermined priority for the processors and the processor having the highest priority is selected from the queue first.

6. A synchronous apparatus for a multi-processor system, comprising:

a spinlock controller for receiving and processing requests for acquiring and releasing a spinlock from a plurality of processors; and

a clock signal generator for providing a plurality of clock signals to the processors, and according to instructions provided by the spinlock controller, suspending the clock signal to a particular processor so that the operation of the processor is suspended in the time period after the processor fails to acquire a spinlock and before the processor successfully acquires the spinlock.

7. The synchronous apparatus of claim 6, wherein the spinlock controller comprises:

a bus interface unit for receiving the requests through a bus matrix;

a control logic unit for receiving the requests from the bus interface unit, processing the requests and maintaining all data related to the spinlock; and

an arbitration unit such that if a particular processor needs to be suspended, the arbitration unit transmits indicating signals to the clock signal generator according to the instructions provided by the control logic unit to suspended the operation of the processor.

8. The synchronous apparatus of claim 7, wherein the related data includes the status of the spinlock and the queue of processors waiting to acquire the spinlock.

9. The synchronous apparatus of claim 8, wherein the spinlock is either in a locked state or in an unlocked state.

10. The synchronous apparatus of claim 8, wherein the related data further includes a predetermined policy and the predetermined policy determines the selection of a processor in the queue having the priority to acquire the spinlock first.

11. The synchronous apparatus of claim 8, wherein the related data further includes a predetermined priority for the processors to acquire the spinlock.

12. The synchronous apparatus of claim 7, wherein the spinlock controller further includes a register group for storing the spinlock related data.

13. The synchronous apparatus of claim 12, wherein the register group further includes:

an acquisition register for storing the status of the spinlock and receiving the requests for acquiring the spinlock;

a releasing register for receiving the requests for releasing the spinlock; and

a queue register for storing all the processors waiting to acquire the spinlock.

14. The synchronous apparatus of claim 13, wherein the register group further includes an arbitration register for storing a predetermined policy, the predetermined policy determines the selection of a processor in the queue having the priority to acquire the spinlock first.

15. The synchronous apparatus of claim 13, wherein the register group further includes a priority register for storing a predetermined priority for the processors to acquire the spinlock.

16. The synchronous apparatus of claim 7, wherein the spinlock controller further comprises a register group for storing a part of the spinlock related data, a memory stores the remaining spinlock related data, and the register group includes an address register for storing the addresses in the memory where the remaining spinlock related data are stored.

17. The synchronous apparatus of claim 16, wherein the memory is either an internal memory included within the spinlock controller or is an independent external memory outside the spinlock controller.

18. The synchronous apparatus of claim 7, wherein the spinlock-related data is stored inside a memory and the spinlock controller further includes an address register for storing the addresses in the memory where the spinlock-related data are stored.

19. The synchronous apparatus of claim 18, wherein the memory is either an internal memory included within the spinlock controller or is an independent external memory outside the spinlock controller.