Integrated memory core and memory interface circuit

• US 20070050530A1
• Filed: 06/23/2006
• Published: 03/01/2007
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh
• Granted Patent: US 7,515,453 B2
• Time in Patent Office: Days
• US Class Current: 711/5
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.

Claims

1. A memory device for use with an external circuit the memory device comprising:

at least one first integrated circuit die including,

a memory core comprising a plurality of memory cells, and

a first interface circuit including a first interface for accessing the memory cells of the memory core; and

at least one second integrated circuit die, electrically coupled to the first integrated circuit die, comprising a second interface for accessing the memory core via the first interface circuit and for interfacing the memory core to the external circuit.

2. The memory device as set forth in claim 1, further comprising:

a plurality of the first integrated circuit dies.

3. The memory device as set forth in claim 1, further comprising:

a plurality of the second integrated circuit dies.

4. The memory device as set forth in claim 1, further comprising:

a first package housing the at least one first integrated circuit die; and

a second package housing the at least one second integrated circuit die.

5. The memory device as set forth in claim 1, further comprising:

a single package housing the first and second integrated circuit dies.

6. The memory device as set forth in claim 1, further comprising:

a plurality of the second integrated circuit dies; and

a single package housing the at least one first integrated circuit die and housing the plurality of second integrated circuit dies.

7. The memory device as set forth in claim 1, further comprising:

a plurality of the first integrated circuit dies; and

a single package housing the plurality of first integrated circuit dies and housing the at least one second integrated circuit die.

8. The memory device as set forth in claim 1, further comprising:

a plurality of the first integrated circuit dies;

a first package for housing the plurality of first integrated circuit dies; and

a second package for housing the at least one second integrated circuit die.

9. The memory device as set forth in claim 1, wherein:

the second interface of the second integrated circuit die further for converting protocols between the external circuit and the first interface of the first integrated circuit die.

10. The memory device as set forth in claim 9, wherein:

the protocols comprise,

a first protocol, and

a second protocol which is different from the first protocol.

11. The memory device as set forth in claim 10, wherein:

the first protocol comprises a synchronous protocol; and

the second protocol comprises an asynchronous protocol.

12. The memory device as set forth in claim 10, wherein:

the first protocol comprises a custom protocol; and

the second protocol comprises an industry standard protocol.

13. The memory device as set forth in claim 1, wherein:

the first interface circuit further for providing a read operation to the memory cells.

14. The memory device as set forth in claim 1, wherein:

the first interface circuit further for providing a write operation to the memory cells.

15. The memory device as set forth in claim 1, wherein:

the first interface circuit further for providing activating, pre-charging and refreshing operations to the memory cells.

16. The memory device as set forth in claim 1, wherein the first integrated circuit die comprises:

a plurality of memory banks for partitioning the memory cells.

17. The memory device as set forth in claim 16, wherein the memory banks comprise:

a plurality of sub-arrays arranged in a distributed bank architecture across a plurality of physical sections such that a physical section of the memory cells comprises a plurality of sub-arrays associated with different ones of the memory banks.

18. The memory device as set forth in claim 1, wherein the memory cells comprise:

at least one non-volatile memory cell.

19. The memory device as set forth in claim 1, wherein the memory cells comprise:

at least one volatile memory cell.

25. The memory device as set forth in claim 9, wherein said second interface of said second integrated circuit die for converting between a DDR2 SDRAM protocol and a DDR3 SDRAM protocol.

26. The memory device as set forth in claim 9, wherein said second interface of said second integrated circuit die for converting between a first timing specification of a DDR2 SDRAM protocol and a second timing specification of a DDR2 SDRAM protocol.

20. A memory device for use with an external circuit, the memory device comprising:

a first integrated circuit die including,

a memory core including a plurality of memory cells, and

a first interface circuit having a first interface and coupled to the memory cells, for dynamically configuring an internal data rate for transferring data between the memory cells and the first interface circuit; and

a second integrated circuit die, electrically coupled to the first integrated circuit die, including a second interface for accessing data from the memory core via the first interface circuit and for interfacing said memory core to the external circuit.

21. The memory device as set forth in claim 20, wherein:

the memory device further comprises an internal data bus for coupling data between the first integrated circuit die and the second integrated circuit die; and

the internal data bus has a configurable data width.

22. The memory device as set forth in claim 20, wherein the internal data rate comprises:

a configurable amount of data for pre-fetching.

23. The memory device as set forth in claim 20, wherein the first integrated circuit die further comprises:

at least one input for programming said data width for said internal data bus.

24. The memory device as set forth in claim 20, further comprising:

an external data bus, having an external data rate, for accessing data external to the memory device, wherein the internal data rate can be dynamically selected so as to be compatible with the external data rate.