FLASH DRIVE FAST WEAR LEVELING

• US 20070050536A1
• Filed: 08/30/2006
• Published: 03/01/2007
• Est. Priority Date: 09/01/2005
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Kolokowsky, Steve
• Granted Patent: US 7,853,749 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A system and method comprising a non-volatile memory including one or more memory blocks to store data, a controller to allocate one or more of the memory blocks to store data, and a wear-leveling table populated with pointers to unallocated memory blocks in the non-volatile memory, the controller to identify one or more pointers in the wear-leveling table and to allocate the unallocated memory blocks associated with the identified pointers for the storage of data.

Claims

1. A system comprising:

a controller to allocate one or more of the memory blocks in a non-volatile memory to store data; and

a wear-leveling table populated with pointers to unallocated memory blocks in the non-volatile memory, the controller to identify one or more pointers in the wear-leveling table and to store data to the memory blocks associated with the identified pointers.

2. The system of claim 1 where the controller is configured erase data stored in one or more of the memory blocks and to populate the wear-leveling table with pointers to the erased memory blocks.

3. The system of claim 2 where the controller is configured to prioritize the pointers in the wear-leveling table according to when the memory blocks associated with the pointers were erased.

4. The system of claim 3 where the controller is configured to linearly search the wear-leveling table for pointers to unallocated memory blocks that are available to store data.

5. The system of claim 4

where the non-volatile memory is NAND-type flash memory;

and

where the wear-leveling table includes 24 pointers to the unallocated memory blocks.

6. The system of claim 1 includes a logical-to-physical table to store pointers to the memory blocks in the non-volatile memory, where the controller initializes the logical-to-physical table with the pointers concurrently to populating the wear-leveling table with pointers to the unallocated memory blocks.

7. The system of claim 6 where the controller is configured to allocate the memory blocks associated with the pointers in the logical-to-physical table prior to the controller accessing the wear-leveling table for pointers to the unallocated memory blocks.

8. The system of claim 1

where the wear-leveling table does not store pointers to the allocated memory blocks;

and

where the unallocated memory blocks were previously erased by the controller.

9. The system of claim 1 where the unallocated memory blocks include one or more memory blocks available to store data and one or more faulty memory blocks not to store data.

10. The system of claim 9 where the wear-leveling table is configured to indicate to the controller which of the pointers are associated with the faulty memory blocks.

11. The system of claim 1 where the non-volatile memory includes multiple memory zones, each memory zone including a plurality of memory blocks and having a different wear-leveling table.

12. A method comprising:

populating a wear-leveling table with pointers to one or more memory blocks in a flash memory, where the pointers are associated with erased memory blocks or memory blocks that are faulty;

identifying at least one pointer in the wear-leveling table; and

storing data to the memory block associated with the identified pointer.

13. The method of claim 12 includes erasing data stored in one or more of the memory blocks responsive to the identifying at least one pointer in the wear-leveling table and prior to storing data to the memory block associated with the identified pointer.

14. The method of claim 12 includes prioritizing the pointers in the wear-leveling table according to when the memory blocks associated with the pointers were erased.

15. The method of claim 14 includes accessing the wear-leveling table for pointers according to the prioritizing.

16. The method of claim 12 includes prioritizing the pointers in the wear-leveling table according to the number of write operations performed on the memory blocks associated with the pointers.

17. The method of claim 12 includes initializing a logical-to-physical table with pointers to the memory blocks in the flash memory concurrently to populating the wear-leveling table with pointers associated with the erased memory blocks.

18. The method of claim 17 includes allocating the memory blocks associated with the pointers in the logical-to-physical table prior to accessing the wear-leveling table for pointers to erased memory blocks.

19. The method of claim 17 includes

receiving a write command identifying a zone of the flash memory to store data;

determining the wear-leveling table does not correspond to the identified zone;

re-populating the wear-leveling table with pointers to memory blocks corresponding to the identified zone.

20. The method of claim 12

identifying erased memory blocks and faulty memory blocks in the flash memory;

comparing the number of identified erased memory blocks and faulty memory blocks to a threshold; and

populating the wear-leveling table responsive to the comparing.

21. The method of claim 12

identifying erased memory blocks and faulty memory blocks in the flash memory;

comparing the number of identified erased memory blocks and faulty memory blocks to a threshold; and

initializing the flash memory with pointers to the memory blocks responsive to the comparing.