Multiprocessor resource optimization

• US 20070050555A1
• Filed: 08/29/2005
• Published: 03/01/2007
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: Searete LLC (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Tegreene, Clarence, Myhrvold, Nathan, Wood, Lowell, Hillis, W.
• Granted Patent: US 7,774,558 B2
• Time in Patent Office: Days
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

Embodiments include a device and a method. In an embodiment, a method applies a first resource management strategy to a first resource associated with a first processor and executes an instruction block in a first processor. The method also applies a second resource management strategy to a second resource of a similar type as the first resource and executes the instruction block in a second processor. The method further selects a resource management strategy likely to provide a substantially optimum execution of the instruction group from the first resource management strategy and the second resource management strategy.

Claims

1. A device comprising:

a first processor having an associated first cache and a second processor having an associated second cache; and

a cache manager implemented in a hardware-logic and operable to

compare an execution of an instruction group by the first processor while a first cache management policy is applied to the associated first cache and an execution of the instruction group by the second processor while a second cache management policy is applied to the associated second cache;

select from the first cache management policy and the second cache management policy a cache management policy likely to provide a substantially optimum execution of the instruction group; and

associate the selected cache management policy with the instruction group.

2. The device of claim 1, wherein the first processor and the second processor are implemented on a single chip.

3. The device of claim 1, wherein the associated first cache and the associated second cache are a logical partition of a physical memory.

4. The device of claim 1, wherein the associated first cache and the associated second cache are accessible by both the first and second processor.

5. The device of claim 1, wherein the associated first cache includes an L2 cache and the associated second cache includes an L2 cache.

6. The device of claim 1, wherein the first processor and the cache manager are formed on a single chip.

7. The device of claim 1, wherein the cache manager operable to associate the selected cache management policy with the instruction group includes a cache manager operable to associate a ghost page indicative of the selected management policy with the instruction group.

8. The device of claim 1, wherein the cache manager operable to compare includes a cache manager operable to compare according to preselected criterion.

10. The device of claim 1, wherein the first cache management policy assumes that the instruction group will execute in a substantially optimal manner.

13. The device of claim 1, wherein the second cache management policy assumes that the instruction group will execute in a substantially sub-optimal manner.

16. The device of claim 1, wherein the cache manager operable to select a management policy likely to provide a substantially optimum execution of the instruction group includes a cache manager operable to select a management policy likely to provide a substantially optimum execution of the instruction group according to a preselected criterion.

18. The device of claim 1, wherein the cache manager operable to select a management policy likely to provide a substantially optimum execution of the instruction group includes a cache manager operable to select a management policy predicted as likely to provide a substantially optimum execution of the instruction group.

19. The device of claim 1, wherein the cache manager operable to select a management policy likely to provide a substantially optimum execution of the instruction group includes a cache manager operable to select a management policy predicted by a Bayesian method as likely to provide a substantially optimum execution of the instruction group.

21. The device of claim 1, wherein the cache manager operable to select a management policy likely to provide a substantially optimum execution of the instruction group includes a cache manager operable to select a management policy predicted by a heuristic as likely to provide a substantially optimum execution of the instruction group.

22. The device of claim 1, wherein the cache manager operable to select a management policy likely to provide a substantially optimum execution of the instruction group includes a cache manager operable to select a management policy predicted by a learning algorithm as likely to provide a substantially optimum execution of the instruction group.

9. (canceled)

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20. (canceled)

23. A device comprising:

a first processor having an associated first hardware resource and a second processor having an associated second hardware resource; and

a resource manager implemented in a hardware-logic and operable to

compare an execution of an instruction group by the first processor while a first resource management policy is applied to the associated first hardware resource and an execution of the instruction group by the second processor while a second resource management policy is applied to the associated second hardware resource;

select from the first resource management policy and the second resource management policy a resource management policy likely to provide a substantially optimum execution of the instruction group; and

associate the selected resource management policy with the instruction group.

24. The device of claim 23, wherein the resource manager is associated with the first processor.

25. The device of claim 23, wherein the resource manager is associated with the first processor and the second processor.

26. The device of claim 23, wherein the associated first hardware resource includes a first branch predictor.

27. The device of claim 23, wherein the associated first hardware resource includes a first branch predictor and the associated second hardware resource includes a second branch predictor.

28. The device of claim 23, wherein the associated first hardware resource includes a first off-processor-chip cache and the associated second hardware resource includes a second off-processor-chip cache.

29. A method comprising:

applying a first resource management strategy to a first resource associated with a first processor and executing an instruction group in the first processor;

applying a second resource management strategy to a second resource of a similar type as the first resource and executing the instruction block in a second processor; and

selecting a resource management strategy likely to provide a substantially optimum execution of the instruction group from the first resource management strategy and the second resource management strategy.

30. The method of claim 29, wherein the applying a first resource management strategy to a first resource associated with a first processor includes applying a first resource management strategy to a cache associated with a first processor.

31. The method of claim 29, wherein the applying a first resource management strategy to a first resource associated with a first processor includes applying a first resource management strategy to a register associated with a first processor.

32. The method of claim 29, wherein the applying a first resource management strategy to a first resource associated with a first processor includes applying a first resource management strategy to a functional unit associated with a first processor.

33. The method of claim 29, wherein the applying a first resource management strategy to a first resource associated with a first processor includes applying a first resource management strategy to a branch predictor associated with a first processor.

34. The method of claim 29, wherein the selecting a resource management strategy likely to provide a substantially optimum execution of the instruction group includes selecting a resource management strategy likely to provide a substantially optimum execution of the instruction group according to preselected criterion.

36. The method of claim 29, wherein the applying a first resource management strategy to a first resource associated with a first processor includes applying an optimistic resource management strategy to a first resource associated with a first processor.

38. The method of claim 29, wherein the applying a second resource management strategy to a second resource of a similar type as the first resource includes applying a pessimistic resource management strategy to a second resource of a similar type as the first resource.

40. The method of claim 29, further comprising:

associating the selected resource management strategy with the instruction group.

41. The method of claim 29, further comprising:

associating a ghost page indicative of the selected resource management strategy with the instruction group.

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43. A device comprising:

a processor having an associated first hardware resource and a present context; and

a control unit associated with the processor and operable to

fetch an instruction for execution by the processor;

receive a previously selected resource management policy associated with the instruction, the previously selected resource management policy selected as likely to provide a substantially optimum execution of an instruction group that includes the instruction, and further selected from an optimistic resource management policy and a pessimistic resource management policy;

apply the previously selected resource management policy if a predetermined similarity exists between the present context of the processor and the context of the processor when the selected resource management policy was selected;

otherwise

do not apply the previously selected resource management policy to the resource; and

cause the processor to execute the instruction.

44. A method comprising:

fetching an instruction to be executed by a processor core of a chip having at least two processor cores that each have access to a resource;

receiving a previously selected resource management policy associated with the instruction, the resource management policy having been selected as likely to provide a substantially optimum execution of an instruction group that includes the instruction, and having further been selected from a optimistic resource management policy and a pessimistic resource management policy;

applying the previously selected resource management policy to the resource; and

executing the instruction by the processor core.

45. The method of claim 44, wherein the fetching an instruction to be executed by a processor core of a chip having at least two processor cores that each have access to a resource includes fetching an instruction to be executed by a processor core of a chip having at least two processor cores that each have access to a cache resource.

47. The method of claim 44, wherein the fetching an instruction to be executed by a processor core of a chip having at least two processor cores that each have access to a resource includes a fetching an instruction to be executed by a processor core of a chip having at least two processor cores that each have access to a branch predictor.

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