Method for maintaining atomicity of instruction sequence to access a number of cache lines during proactive synchronization within a computer system

• US 20070050559A1
• Filed: 08/23/2006
• Published: 03/01/2007
• Est. Priority Date: 08/23/2005
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Alsup, Mitchell
• Granted Patent: US 7,552,290 B2
• Time in Patent Office: Days
• US Class Current: 711/145
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A method for maintaining atomicity of a sequence of instructions includes a processor requesting exclusive access to a given memory resource. The request may include executing a critical section of code having memory reference instructions each including a LOCK prefix, and the memory reference instructions may be followed by an ACQUIRE instruction. The method also includes comparing each memory address of the critical section of code to each address of sets of addresses in response to execution of the ACQUIRE instruction. Each address of the sets of addresses corresponds to a respective memory resource to which a requester has exclusive access. In response to any memory address of the critical section of code matching any address of the sets of addresses, the method includes causing the ACQUIRE instruction to fail, and inhibiting modifying data corresponding to any memory address in an atomic phase of the critical section of code.

Claims

1. A method comprising:

a processor requesting exclusive access to a given memory resource, wherein the request includes executing a critical section of code having a one or more memory reference instructions each having a LOCK prefix followed by an ACQUIRE instruction, wherein during the specification phase, each memory reference instruction specifies a memory address associated with the given memory resource;

in response to execution of the ACQUIRE instruction, comparing each memory address specified in the critical section of code to each address of a plurality of sets of addresses, wherein each address of the plurality of sets of addresses corresponds to a respective memory resource to which a requestor has been granted exclusive access; and

in response to any memory address of the critical section of code matching any address of a plurality of sets of addresses, causing the ACQUIRE instruction to fail; and

inhibiting modifying data corresponding to any memory address in an atomic phase of the critical section of code.

2. The method as recited in claim 1, further comprising in response to no memory address of the critical section of code matching any address in the plurality of sets of addresses, generating a success indication that then enables entering the atomic phase, modifying data corresponding to all memory addresses in the atomic phase of the critical section of code, and releasing all memory addresses in the critical section of code for use by other processors upon completion of the modification.

3. The method as recited in claim 1, further comprising causing the ACQUIRE instruction to fail, and inhibiting modifying data corresponding to any memory address in the atomic phase of the critical section of code in response to receiving a PROBE message corresponding to any memory address specified in the specification phase of the critical section of code prior to receiving an indication of whether any memory address of the critical section of code matches any address of the plurality of sets of addresses.

4. The method as recited in claim 1, further comprising responding to a received PROBE message corresponding to any memory address of the critical section of code with a failure message in response to receiving an indication that no memory address of the critical section of code matches any address in the plurality of sets of addresses.

5. The method as recited in claim 1, wherein the indication that no memory address of the critical section of code matches any address in the plurality of sets of addresses comprises a pass count value of zero.

6. The method as recited in claim 1, further comprising modifying a particular condition code register flag in response receiving an indication that a memory address of the critical section of code matches any address of the plurality of sets of addresses.

7. The method as recited in claim 6, wherein causing the ACQUIRE instruction to fail includes branching out of the critical section of code by executing a subsequent conditional jump instruction based upon the particular condition code register flag value.

8. The method as recited in claim 6, wherein in response to accepting an enabled interrupt, causing the ACQUIRE instruction to fail by modifying a particular condition code register flag and branching out of the critical section of code by executing a subsequent conditional jump instruction based upon the particular condition code register flag value.

9. The method as recited in claim 1 wherein causing the ACQUIRE instruction to fail includes notifying a retire circuit within the processor that the ACQUIRE instruction has failed.

10. A computer system comprising:

a plurality of processors coupled together and to one or more memories, wherein each of the processors is configured to execute instructions to request exclusive access to a given memory resource, wherein the request includes a specification phase of a critical section of code having a one or more memory reference instructions having a LOCK prefix followed by an ACQUIRE instruction, wherein each memory reference instruction specifies a memory address associated with the given memory resource; and

an arbitration unit coupled to compare each memory address of the specification phase the critical section of code to each address of a plurality of sets of addresses in response to execution of the ACQUIRE instruction, wherein each address of the plurality of sets of addresses corresponds to a respective memory resource to which a requestor has been granted exclusive access;

wherein in response to any memory address of the critical section of code matching any address of a plurality of sets of addresses, each of the processors is configured to;

cause the ACQUIRE instruction to fail; and

inhibit modifying data corresponding to any memory address in an atomic phase of the critical section of code.

11. The computer system as recited in claim 10, wherein in response to no memory address of the critical section of code matching any address in the plurality of sets of addresses, a given processor of the plurality of processors is configured to:

generate a success indication that then enables entering the atomic phase, modify data corresponding to all memory addresses in the atomic phase of the critical section of code, and release all memory addresses in the critical section of code for use by other processors upon completion of the modification.

12. The computer system as recited in claim 10, wherein each of the processors is configured to cause the ACQUIRE instruction to fail, and to inhibit modifying data corresponding to any memory address in the atomic phase of the critical section of code in response to receiving a PROBE message corresponding to any memory address of the critical section of code prior to receiving an indication of whether any memory address of the critical section of code matches any address of the plurality of sets of addresses.

13. The computer system as recited in claim 10, wherein a given processor of the plurality of processors is configured to respond to a received PROBE message corresponding to any memory address of the critical section of code with a failure message in response to receiving an indication that no memory address of the critical section of code matches any address in the plurality of sets of addresses.

14. The computer system as recited in claim 10, wherein the indication that no memory address of the critical section of code matches any address in the plurality of sets of addresses comprises a pass count value of zero.

15. The computer system as recited in claim 10, wherein each of the processors is configured to modify a particular condition code register flag in response receiving an indication that a memory address of the critical section of code matches any address of the plurality of sets of addresses.

16. The computer system as recited in claim 15, wherein each of the processors is configured to branch out of the critical section of code by executing a conditional jump instruction subsequent to the ACQUIRE instruction based upon the particular condition code register flag value.

17. The computer system as recited in claim 15, wherein in response to accepting an enabled interrupt, each processor is configured to cause the ACQUIRE instruction to fail by modifying a particular condition code register flag and branching out of the critical section of code by executing a subsequent conditional jump instruction based upon the particular condition code register flag value.

18. The computer system as recited in claim 10, wherein each of the processors is configured to cause the ACQUIRE instruction to fail by notifying a respective retire circuit within each processor that the ACQUIRE instruction has failed.