Synchronization arbiter for proactive synchronization within a multiprocessor computer system

• US 20070050563A1
• Filed: 08/23/2006
• Published: 03/01/2007
• Est. Priority Date: 08/23/2005
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Alsup, Mitchell
• Application Number:
  US11/508,647
• Publication Number:
  US 20070050563A1
• Time in Patent Office: Days
• US Class Current: 711/145
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A synchronization arbiter may be used in a computer system including one or more processors configured to request exclusive access to a given memory resource. The request may include one or more addresses associated with the memory resource. The synchronization arbiter includes an address storage that may store sets of addresses. Each address may correspond to a respective memory resource to which a requestor has acquired exclusive access. The address storage may further store count values, each associated with a respective set of addresses, and each may be indicative of a number of requesters contending for any address in the respective set of addresses. If any of the one or more addresses matches any address in the sets of addresses, control logic may return the count value associated with the matching address to the requestor.

Claims

1. A synchronization arbiter for use in a computer system including one or more processors each configured to request exclusive access to a given memory resource, wherein the request includes one or more addresses associated with the given memory resource, the synchronization arbiter comprising:

an address storage configured to store a plurality of sets of addresses, wherein each address of the plurality of sets of addresses corresponds to a respective memory resource to which a requester has acquired exclusive access;

wherein the address storage is further configured to store a plurality of count values each associated with a respective set of addresses of the plurality of sets of addresses, wherein each count value is indicative of a number of requestors contending for any address in each respective set of addresses;

a compare unit coupled to the address storage and configured to compare each of the one or more addresses in the request to each address of the plurality of sets of addresses stored in the address storage; and

control logic coupled to the compare unit and configured to return to the requester, the count value associated with a matching address in response to any address of the one or more addresses matching any address in the plurality of sets of addresses.

2. The synchronization arbiter as recited in claim 1, wherein the control logic is further configured to return to the requestor, a predetermined count value in response to no address of the one or more addresses matching any address in the plurality of sets of addresses.

3. The synchronization arbiter as recited in claim 2, wherein the predetermined count value comprises a pass count value of zero.

4. The synchronization arbiter as recited in claim 1, wherein the control logic is further configured to store the one or more addresses within the address storage in response to no address of the one or more addresses matching any address in the plurality of sets of addresses.

5. The synchronization arbiter as recited in claim 1, wherein the address storage comprises a plurality of entries, wherein each entry is configured to store one set of the plurality of sets of addresses and the associated count value.

6. The synchronization arbiter as recited in claim 1, wherein each address corresponds to a physical address of a 64-byte cache line.

7. The synchronization arbiter as recited in claim 1, wherein each set of addresses of the plurality of sets of addresses comprises up to eight physical addresses.

8. The synchronization arbiter as recited in claim 1, wherein the control logic is further configured to remove a set of addresses from the address storage in response to receiving a notification of completion of operations on corresponding data in the given memory resource.

9. The synchronization arbiter as recited in claim 1, wherein the control logic is further configured to increase the count value associated with the set of addresses including the matching address prior to returning the count value.

10. The synchronization arbiter as recited in claim 1, further comprising one or more communications interfaces for connection to the one or more processors via one or more communications links.

11. The synchronization arbiter as recited in claim 10, wherein the one or more communications links comprise pairs of unidirectional packet-based links.

12. A computer system comprising:

one or more processors coupled together and to one or more memories, wherein each of the processors is configured to request exclusive access to a given memory, wherein the request includes one or more addresses associated with the given memory; and

a synchronization arbiter coupled to each of the one or more processors, wherein the synchronization arbiter includes;

an address storage configured to store a plurality of sets of addresses, wherein each address of the plurality of sets of addresses corresponds to a respective memory to which a requester has acquired exclusive access;

wherein the address storage is further configured to store a plurality of count values each associated with a respective set of addresses of the plurality of sets of addresses, wherein each count value is indicative of a number of requesting processors contending for any address in each respective set of addresses;

a compare unit coupled to the address storage and configured to compare each of the one or more addresses in the request to each address of the plurality of sets of addresses stored in the address storage; and

control logic coupled to the compare unit and configured to return to the requesting processor, the count value associated with a matching address in response to any address of the one or more addresses matching any address in the plurality of sets of addresses.

13. The computer system as recited in claim 12, wherein the control logic is further configured to return to the requestor, a predetermined count value in response to no address of the one or more addresses matching any address in the plurality of sets of addresses.

14. The computer system as recited in claim 13, wherein the predetermined count value comprises a pass count value of zero.

15. The computer system as recited in claim 12, wherein the control logic is further configured to store the one or more addresses within the address storage in response to no address of the one or more addresses matching any address in the plurality of sets of addresses.

16. The computer system as recited in claim 12, wherein the address storage comprises a plurality of entries, wherein each entry is configured to store one set of the plurality of sets of addresses and the associated count value.

17. The computer system as recited in claim 12, wherein each address corresponds to a physical address of a 64-byte cache line.

18. The computer system as recited in claim 12, wherein each set of addresses of the plurality of sets of addresses comprises up to eight physical addresses.

19. The computer system as recited in claim 12, wherein the control logic is further configured to remove a set of addresses from the address storage in response to receiving a notification of completion of operations on corresponding data in the given memory resource.

20. The computer system as recited in claim 12, wherein the control logic is further configured to increase the count value associated with the set of addresses including the matching address prior to returning the count value.

21. The computer system as recited in claim 12, wherein the one or more processors and the synchronization arbiter are interconnected via a plurality of communications links each comprising a pair of unidirectional packet-based links

22. The computer system as recited in claim 12, wherein each of the one or more processors is further configured to use the count value to request exclusive access to a different memory resource including a different set of addresses.

23. A synchronization arbiter for use in a computer system including one or more processors each configured to request exclusive access to a given memory resource, wherein the request includes one or more addresses associated with the given memory resource, the synchronization arbiter comprising:

an address storage configured to store a plurality of sets of addresses, wherein each address of the plurality of sets of addresses corresponds to a respective memory resource to which a requestor has acquired exclusive access;

wherein the address storage is further configured to store a plurality of count values, each count value associated with a respective address of each set of the plurality of sets of addresses, wherein each count value is indicative of a number of requestors contending for the associated respective address;

a compare unit coupled to the address storage and configured to compare each of the one or more addresses in the request to each address of the plurality of sets of addresses stored in the address storage; and

control logic coupled to the compare unit and configured to return to the requester, the count value associated with a matching address in response to any address of the one or more addresses matching any address in the plurality of sets of addresses.

24. The synchronization arbiter as recited in claim 23, wherein the control logic is further configured to store the one or more addresses, as a set, within the address storage in response to no address of the one or more addresses matching any address in the plurality of sets of addresses.

25. The synchronization arbiter as recited in claim 23, wherein the control logic is further configured to store the one or more addresses using a sequence of store operations within the address storage in response to no address of the one or more addresses matching any address in the plurality of sets of addresses.

26. The synchronization arbiter as recited in claim 23, wherein the control logic is further configured to remove a set of addresses from the address storage in response to receiving a notification of completion of operations on corresponding data in the given memory resource.

27. The synchronization arbiter as recited in claim 23, wherein the control logic is further configured to remove addresses from the address storage in a sequence of operations in response to receiving a notification of completion of operations on corresponding data in the given memory resource.