Fetch rerouting in response to an execution-based optimization profile

• US 20070050604A1
• Filed: 11/30/2005
• Published: 03/01/2007
• Est. Priority Date: 08/29/2005
• Status: Abandoned Application

• Current Assignee: Searete LLC (Intellectual Ventures LLC)
• Original Assignee: Searete LLC (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Tegreene, Clarence, Myhrvold, Nathan, Wood, Lowell, Hillis, W., Mangione-Smith, William
• Application Number:
  US11/291,503
• Publication Number:
  US 20070050604A1
• Time in Patent Office: Days
• US Class Current: 712/226
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 8/443 Optimisation

Abstract

Embodiments include a device, and a method. In an embodiment, a device includes a processor operable to execute an instruction set, and an execution-optimization circuit. The execution circuit includes an execution circuit for receiving an identification of a first instruction to be fetched from the instruction set for execution by the processor, and for pointing to a second instruction of the instruction set of the processor to be fetched for execution by the processor if indicated by an execution-based optimization profile. The execution-based optimization profile being previously derived by a hardware device utilizing data invisible to software and generated during a runtime execution of at least a portion of the instruction set. The execution-optimization circuit may include at least one of a microengine, a micro-programmed circuit, and/or a hardwired circuit.

Claims

1. A device comprising:

a processor operable to execute an instruction set;

an execution-optimization circuit for

receiving an identification of a first instruction to be fetched from the instruction set for execution by the processor; and

pointing to a second instruction of the instruction set of the processor to be fetched for execution by the processor if indicated by an execution-based optimization profile,

the execution-based optimization profile being previously derived by a hardware device utilizing data invisible to software and generated during a runtime execution of at least a portion of the instruction set.

2. The device of claim 1, wherein the execution-optimization circuit includes at least one of a microengine, a micro-programmed circuit, and/or a hardwired circuit.

3. The device of claim 1, wherein the execution-optimization circuit includes an execution-optimization portion of a control unit of the processor.

4. The device of claim 1, wherein the processor and the execution-optimization circuit are formed on a chip.

5. The device of claim 1, wherein the execution-optimization circuit for receiving an identification of a first instruction to be fetched from the instruction set for execution by the processor includes an execution-optimization circuit for receiving an identification of a first instruction to be fetched from the instruction set of a static program for execution by the processor.

6. The device of claim 1, wherein the execution-optimization circuit for pointing to a second instruction of the instruction set of the processor to be fetched for execution by the processor if indicated by an execution-based optimization profile includes

an execution-optimization circuit for pointing to a second instruction of the instruction set of the processor to be fetched for execution by the processor if indicated by an execution-based optimization profile associated with the first instruction.

7. The device of claim 1, wherein the execution-optimization circuit for pointing to a second instruction of the instruction set of the processor to be fetched for execution by the processor if indicated by an execution-based optimization profile includes

an execution-optimization circuit for pointing to a second instruction of the instruction set of the processor to be fetched for execution by the processor if indicated by an execution-based optimization profile associated with another instruction of the instruction set.

8. The device of claim 1, wherein the execution-based optimization profile being previously derived by a hardware device utilizing data invisible to software and generated during a runtime execution of at least a portion of the instruction set includes

the execution-based optimization profile being previously derived by a hardware device utilizing data invisible to software and generated during a runtime execution of at least a portion of an instruction set of a static program.

9. A method transparent to software executing on a processor, the method comprising:

in response to an identification of a first instruction to be fetched for execution by a processor, fetching a second instruction for execution by the processor if indicated by an execution-based optimization profile,

the execution-based optimization profile previously derived by a hardware device utilizing data invisible to software and generated during a runtime execution of at least a portion of the instruction set.

10. The method of claim 9, further comprising:

identifying the first instruction to be fetched for execution by the processor.

11. The method of claim 9, wherein the in response to an identification of a first instruction to be fetched for execution by the processor, fetching a second instruction for execution by the processor if indicated by an execution-based optimization profile includes

in response to an identification of a first instruction to be fetched from an instruction set of a static program for execution by the processor, fetching the second instruction for execution by the processor if indicated by an execution-based optimization profile.

12. The method of claim 9, wherein the fetching a second instruction for execution by the processor if indicated by an execution-based optimization profile includes

fetching the second instruction from an instruction set of a static program for execution by the processor if indicated by an execution-based optimization profile.

13. The method of claim 9, wherein the fetching a second instruction for execution by the processor if indicated by an execution-based optimization profile includes

fetching the second instruction from an instruction set of the processor for execution by the processor if indicated by an execution-based optimization profile.

14. The method of claim 9, wherein the fetching a second instruction for execution by the processor if indicated by an execution-based optimization profile includes

fetching the second instruction of the instruction set of a static program if indicated by an execution-based optimization profile linked to the first instruction.

15. The device of claim 9, wherein the fetching a second instruction for execution by the processor if indicated by an execution-based optimization profile includes

fetching the second instruction for execution by the processor if indicated by an execution-based optimization profile linked to the first instruction.

16. The device of claim 9, wherein the fetching a second instruction for execution by the processor if indicated by an execution-based optimization profile includes

fetching the second instruction for execution by the processor if indicated by an execution-based optimization profile saved in a cache operably coupled with the processor.

17. The device of claim 9, wherein the execution-based optimization profile previously derived by a hardware device utilizing data invisible to software and generated during a runtime execution of at least a portion of the instruction set includes

the execution-based optimization profile being previously derived by a hardware device utilizing data invisible to software and generated during a runtime execution of the first instruction.

18. The method of claim 9, further comprising:

otherwise, fetching the first instruction from the instruction set of a static program for execution by the processor.

19. A device comprising:

means for selecting a first instruction to be fetched from an instruction set of a static program for execution by a processor;

means for routing the fetch of the first instruction to a second instruction of the instruction set of a static program if indicated by an execution-based optimization profile,

the execution-based optimization profile having been derived from data invisible to software and generated during a historical execution of the static program.