Alteration of execution of a program in response to an execution-optimization information

• US 20070050607A1
• Filed: 11/30/2005
• Published: 03/01/2007
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Tegreene, Clarence, Myhrvold, Nathan, Wood, Lowell, Hillis, W., Mangione-Smith, William
• Granted Patent: US 8,402,257 B2
• Time in Patent Office: Days
• US Class Current: 712/227
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 8/443 Optimisation

Abstract

Embodiments include a device, and a method. In an embodiment, a device includes an information store operable to save an execution-optimization information, a first processor, and a hardware circuit. The hardware circuit includes a hardware circuit for altering an execution of a program by the first processor in response to the execution-optimization information. The execution-optimization information created by a hardware device utilizing data collected from a second processor and corresponding to a previous runtime execution by the second processor of at least a portion of the program that was transparent to any software executing on the second processor.

Claims

1. A device comprising:

an information store operable to save an execution-optimization information;

a first processor; and

a hardware circuit for altering an execution of a program by the first processor in response to the execution-optimization information,

the execution-optimization information created by a hardware device utilizing data collected from a second processor and corresponding to a previous runtime execution by the second processor of at least a portion of the program that was transparent to any software executing on the second processor.

2. The device of claim 1, wherein the first processor includes

a first processor operable to execute an instruction set and operably coupled to the information store.

3. The device of claim 1, wherein the hardware circuit for altering an execution of a program includes

a hardware circuit for altering an execution of a program and operably coupled to the information store.

4. The device of claim 1, wherein the hardware circuit includes a hardware circuit operably coupled to the processor.

5. The device of claim 1, wherein the hardware circuit includes a hardware circuit for copying the execution-optimization information from the information store to a memory operably coupled to the first processor.

6. The device of claim 1, wherein the hardware circuit for altering an execution of a program by the first processor in response to the execution-optimization information includes

a hardware circuit for altering an execution of at least one instruction of an instruction set of a static program by the first processor in response to the execution-optimization information.

7. The device of claim 1, wherein the hardware circuit for altering an execution of a program by the first processor in response to the execution-optimization information includes

a hardware circuit for altering an execution of at least one instruction of an instruction set of a dynamic program by the first processor in response to the execution-optimization information.

8. The device of claim 1, wherein the hardware circuit for altering an execution of a program by the first processor in response to the execution-optimization information includes

a hardware circuit for altering an execution of at least one instruction of an instruction set of a program by the first processor in response to the execution-optimization information.

9. The device of claim 1, wherein the hardware circuit for altering an execution of a program by the first processor in response to the execution-optimization information includes

a hardware circuit for altering a movement of data with respect to the first processor in response to the execution-optimization information.

10. The device of claim 1, wherein the hardware circuit for altering an execution of a program by the first processor in response to the execution-optimization information includes

a hardware circuit for altering a movement of at least one instruction of the program toward the first processor in response to the execution-optimization information.

11. The device of claim 1, wherein the execution-optimization information created by a hardware device utilizing data collected from a second processor includes

the execution-optimization information created by a hardware device utilizing data collected from a second processor that is at least substantially a same processor as the first processor.

12. The device of claim 1, wherein the execution-optimization information created by a hardware device utilizing data collected from a second processor includes

an execution-optimization information created by a hardware device utilizing data collected from a second processor that is at least a substantially different processor from the first processor.

13. The device of claim 1, wherein the information store includes a computer readable medium.

14. The device of claim 1, wherein the information store includes at least a portion of a cache.

15. The device of claim 1, wherein the information store includes at least one of an I-cache or a D-cache.

16. The device of claim 1, wherein the information store includes at least one of a volatile memory or a non-volatile memory.

17. The device of claim 1, wherein the first processor and the hardware circuit are formed on a single chip.

18. A method comprising:

identifying an instruction to be fetched for execution by a first processor; and

altering an execution of the instruction to be fetched for execution in response to an execution-optimization information,

the execution-optimization information previously generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor.

19. The method of claim 18, wherein the identifying an instruction to be fetched for execution by a first processor includes

identifying an instruction to be fetched from an instruction set of a static program for execution by a first processor.

20. The method of claim 18, wherein the altering an execution of the instruction to be fetched for execution in response to an execution-optimization information includes

altering an execution of the instruction to be fetched from an instruction set of a static program for execution in response to an execution-optimization information.

21. The method of claim 18, wherein the execution-optimization information generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor includes

the execution-optimization information having been previously generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor, the second processor being at least a substantially same processor as the first processor.

22. The method of claim 18, wherein the execution-optimization information generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor includes

the execution-optimization information having been previously generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor, the second processor being at least a substantially different processor from the first processor.

23. The method of claim 18, wherein the execution-optimization information generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor includes

the execution-optimization information having been previously generated by a hardware device utilizing data corresponding to a state of the second processor during a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor.

24. The method of claim 18, wherein the execution-optimization information generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor includes

the execution-optimization information having been previously generated by a hardware device utilizing data corresponding to an instruction state during a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor.

25. The method of claim 18, wherein the execution-optimization information generated by a hardware device utilizing data corresponding to a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor includes

the execution-optimization information having been previously generated by a hardware device utilizing data corresponding to a data relationship during a real execution of the instruction to be fetched by a second processor that was transparent to software executing on the second processor.

26. A device comprising:

means for identifying an instruction to be fetched from an instruction set of a program for execution by a first processor; and

means for altering an execution of the instruction from the instruction set of a program in response to an execution-optimization information,

the execution-optimization information having been generated by a hardware device utilizing data generated by a second processor, and which data corresponds to a previous real execution the instruction to be fetched from the instruction set of a program that was transparent to software executing on the second processor.