Hardware-generated and historically-based execution optimization

• US 20070050608A1
• Filed: 11/30/2005
• Published: 03/01/2007
• Est. Priority Date: 08/29/2005
• Status: Abandoned Application

• Current Assignee: Searete LLC (Intellectual Ventures LLC)
• Original Assignee: Searete LLC (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Tegreene, Clarence, Myhrvold, Nathan, Wood, Lowell, Hillis, W., Mangione-Smith, William
• Application Number:
  US11/292,323
• Publication Number:
  US 20070050608A1
• Time in Patent Office: Days
• US Class Current: 712/227
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 8/443 Optimisation

Abstract

Embodiments include a device, and a method. In an embodiment, a device includes a processor operable to execute an instruction set, a communications link exposed to an execution-optimization synthesizer and to the processor, and the execution-optimization synthesizer. The execution-optimization optimization synthesizer includes an execution-optimization synthesizer operable to collect data from the communications link that corresponds to an execution of at least one instruction of the instruction set, and generate an execution-optimization information utilizing the collected data from the communications link and corresponding to the execution of at least one instruction of the instruction set.

Claims

1. A device comprising:

a processor operable to execute an instruction set;

a communications link exposed to an execution-optimization synthesizer and to the processor; and

the execution-optimization synthesizer operable to;

collect data from the communications link that corresponds to an execution of at least one instruction of the instruction set; and

generate an execution-optimization information utilizing the collected data from the communications link and corresponding to the execution of at least one instruction of the instruction set.

2. The device of claim 1, wherein the instruction set includes an instruction set of a static program.

3. The device of claim 1, wherein the instruction set includes an instruction set of an instruction set architecture.

4. The device of claim 1, wherein the communications link includes at least one of a signal-bearing medium, a light propagation medium, an optical fiber, a light guide, a computer readable storage medium, a hardware register, a bus, an interconnection structure, and/or a signal conductor.

5. The device of claim 1, wherein the communications link exposed to an execution-optimization synthesizer and to the processor includes

a communications link exposed only to an execution-optimization synthesizer and the processor.

6. The device of claim 1, wherein the communications link exposed to an execution-optimization synthesizer and to the processor includes

a communications link exposed to an execution-optimization synthesizer and the processor, and transparent to software executing on the processor.

7. The device of claim 1, wherein the communications link exposed to an execution-optimization synthesizer and to the processor includes

a communications link exposed to an execution-optimization synthesizer, to the processor, and to software.

8. The device of claim 1, wherein the processor and the communications link reside on a single chip.

9. The device of claim 1, wherein the processor and the execution-optimization synthesizer reside on a single chip.

10. The device of claim 1, wherein the processor, communications link, and the execution-optimization synthesizer are formed on a single chip.

11. The device of claim 1, wherein the execution-optimization synthesizer includes a hardware-implemented execution-optimization synthesizer.

12. The device of claim 1, wherein the execution-optimization synthesizer includes a microengine-implemented execution-optimization synthesizer.

13. The device of claim 1, wherein the execution-optimization synthesizer operable to collect data from the communications link that corresponds to an execution of at least one instruction of the instruction set includes

an execution-optimization synthesizer operable to collect dynamic data from the communications link that corresponds to a runtime execution of at least one instruction of the instruction set.

14. The device of claim 1, wherein the execution-optimization synthesizer operable to collect data from the communications link that corresponds to an execution of at least one instruction of the instruction set includes

an execution-optimization synthesizer operable to collect data that includes at least one of a translated instruction of the instruction set, a decoded instruction of the instruction set, a micro-operation corresponding to at least a portion of the at least one instruction of the instruction set, data correlating to an execution of the at least one instruction of the instruction set, a movement of data correlating to an execution of the at least one instruction of the instruction set, a result of an execution of the at least one instruction of the instruction set, a branch outcome of an execution of the at least one instruction of the instruction set, an exception correlating to an execution of the at least one instruction of the instruction set, a store-to-load dependency correlating an execution of the at least one instruction of the instruction set, a predicted value correlating to an execution of the at least one instruction of the instruction set, and/or a relationship between at least two instructions of the instruction set.

15. The device of claim 1, wherein the execution-optimization synthesizer operable to collect data from the communications link that corresponds to an execution of at least one instruction of the instruction set includes

an execution-optimization synthesizer operable to collect at least one of data transparent to a user, data visible to a user, data transparent to software executing on the processor, data visible to software executing on the processor, and/or data exposed for user manipulation.

16. The device of claim 1, wherein the execution-optimization synthesizer operable to generate an execution-optimization information utilizing the collected data includes

an execution-optimization synthesizer operable to generate an optimization information that is at least one of responsive to the collected data, derived from the collected data, associated with the collected data, and/or using the collected data.

17. The device of claim 1, wherein the execution-optimization synthesizer operable to generate an execution-optimization information corresponding to the execution of at least one instruction of the instruction set includes

an execution-optimization synthesizer operable to generate at least one of an execution-environment optimization information, a processor-environment optimization information, a data-environment optimization information, and/or a metadata reporting an execution environment.

18. The device of claim 1, wherein the execution-optimization synthesizer further includes an execution-optimization synthesizer operable to save the optimization information.

19. The device of claim 1, wherein the execution-optimization synthesizer further includes an execution-optimization synthesizer operable to save the optimization information in an association with the at least one instruction of the instruction set.

20. The device of claim 1, wherein the device includes a computing device.

21. The device of claim 20, wherein the computing device includes at least one of desktop computing device, a laptop computing device, a portable computing device, and/or a supercomputing device.

22. A method comprising:

collecting data corresponding to an execution of at least one instruction of an instruction set from a processor executing the at least one instruction of an instruction set;

creating an execution-optimization information utilizing the collected data corresponding to the execution of at least one instruction of the instruction set and which is usable in another execution of the at least one instruction of an instruction set.

23. The method of claim 22, wherein the collecting data corresponding to an execution of at least one instruction of an instruction set from a processor executing the at least one instruction of an instruction set includes

collecting data corresponding to an execution of at least one instruction of an instruction set from a processor actually executing the at least one instruction of an instruction set.

24. The method of claim 22, wherein the collecting data corresponding to an execution of at least one instruction of an instruction set from a processor executing the at least one instruction of an instruction set includes

collecting data corresponding to a runtime execution of at least one instruction of an instruction set from a processor executing the at least one instruction of an instruction set.

25. The method of claim 22, wherein the creating an execution-optimization information utilizing the collected data corresponding to the execution of at least one instruction of the instruction set and which is usable in another execution of the at least one instruction of an instruction set includes

creating a modification of the at least one instruction of the instruction set usable in another execution of the at least one instruction of an instruction set.

26. The method of claim 22, wherein the creating an execution-optimization information utilizing the collected data corresponding to the execution of at least one instruction of the instruction set and which is usable in another execution of the at least one instruction of an instruction set includes

creating a branch predictor modification usable in another execution of the at least one instruction of an instruction set.

27. The method of claim 22, wherein the creating an execution-optimization information utilizing the collected data corresponding to the execution of at least one instruction of the instruction set and which is usable in another execution of the at least one instruction of an instruction set includes

creating a data format modification usable in another execution of the at least one instruction of an instruction set.

28. The method of claim 22, wherein the creating an execution-optimization information utilizing the collected data corresponding to the execution of at least one instruction of the instruction set and which is usable in another execution of the at least one instruction of an instruction set includes

creating a data layout optimization usable in another execution of the at least one instruction of an instruction set.

29. A device comprising:

a first circuit for collecting data corresponding to a runtime execution of at least one instruction of an instruction set from a communications link that is transparent to software and exposed to a processor having a processor instruction set that includes the instruction set; and

a second circuit for creating an execution-optimization information utilizing the collected data corresponding to the execution of at least one instruction of the instruction set and which is usable in another execution of the at least one instruction of an instruction set.

30. The device of claim 29, wherein the circuit for creating the execution-optimization information includes the circuit for collecting data corresponding to an execution.