Cross-architecture execution optimization

• US 20070050609A1
• Filed: 01/31/2006
• Published: 03/01/2007
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: Searete LLC (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Tegreene, Clarence, Myhrvold, Nathan, Wood, Lowell, Hillis, W., Mangione-Smith, William
• Granted Patent: US 8,214,191 B2
• Time in Patent Office: Days
• US Class Current: 712/227
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring

Abstract

Embodiments include a device, apparatus, and a method. A device includes an input circuit for receiving data corresponding to a runtime execution of a first instruction by a first processor having a first architecture. The device also includes a generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture.

Claims

1. A device comprising:

an input circuit for receiving data corresponding to a runtime execution of a first instruction by a first processor having a first architecture; and

a generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture.

2. The device of claim 1, wherein the input circuit for receiving data corresponding to a runtime execution of a first instruction by a first processor having a first architecture includes

an input circuit for receiving data corresponding to a runtime execution of a first instruction by a first processor having a first instruction set architecture.

3. The device of claim 1, wherein the input circuit for receiving data corresponding to a runtime execution of a first instruction by a first processor having a first architecture includes

an input circuit for receiving data corresponding to a runtime execution of a first instruction by a first processor having a first microarchitecture.

4. The device of claim 1, wherein the input circuit for receiving data corresponding to a runtime execution of a first instruction by a first processor having a first architecture includes

an input circuit for receiving data corresponding to a runtime execution of a first instruction associated with a program by a first processor having a first architecture.

5. The device of claim 4, wherein the generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture includes

a generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction associated with the program by a second processor having a second architecture.

6. The device of claim 1, wherein the input circuit for receiving data corresponding to a runtime execution of a first instruction by a first processor having a first architecture includes

an input circuit for receiving data corresponding to a runtime execution of a first instruction associated with an application by a first processor having a first architecture.

7. The device of claim 1, wherein the input circuit for receiving data corresponding to a runtime execution of a first instruction by a first processor having a first architecture includes

an input circuit for receiving data transparent to software executing on the first processor and corresponding to a runtime execution of a first instruction by the first processor having a first architecture.

8. The device of claim 1, wherein the generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture includes

a generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second instruction set architecture.

9. The device of claim 1, wherein the generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture includes

a generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction associated by a second processor having a second microarchitecture.

10. The device of claim 1, wherein the generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture includes

a generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture, the second instruction being at least substantially similar to the first instruction.

11. The device of claim 1, wherein the generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture includes

a generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture, the second instruction being at least substantially different from the first instruction.

12. The device of claim 1, wherein the generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture includes

a generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture in response to the received data.

13. The device of claim 1, wherein the generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture includes

a generator circuit for creating an execution-based optimization profile useable in prefetching data in conjunction with an execution of a second instruction by a second processor having a second architecture.

14. The device of claim 1, wherein the generator circuit for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture includes

a generator circuit for creating an execution-based optimization profile useable in prefetching a third instruction in conjunction with an execution of a second instruction by a second processor having a second architecture.

15. The device of claim 1, wherein the first instruction includes at least one of a machine-level instruction, a compiled instruction, a compilable instruction, one instruction, at least two instructions, an instruction line, an instruction block, an atomic instruction block, a program, and/or an application.

16. The device of claim 1, wherein the first processor includes an x86 architecture and the second processor includes a PowerPC architecture.

17. The device of claim 1, wherein the first processor includes an Intel based architecture and the second processor includes an AMD based architecture.

18. The device of claim 1, further comprising:

an information store configured by the execution-based optimization profile.

19. The device of claim 1, further comprising:

an output circuit for broadcasting the execution-based optimization profile.

20. A device comprising:

means for receiving data transparent to software executing on a first processor having a first architecture and corresponding to a runtime execution of a first instruction by the first processor; and

means for creating an execution-based optimization profile useable in an execution of a second instruction by a second processor having a second architecture.

21. The device of claim 20, further comprising:

means for configuring an information store in response to the execution-based optimization profile.

22. An apparatus comprising:

an input module operable to receive data transparent to software executing on a first processor having a first instruction set architecture and corresponding to a runtime execution of a first instruction by the first processor; and

a generator module operable to create an execution optimization information useable in an execution of a second instruction by a second processor having a second instruction set architecture.

23. The apparatus of claim 22, wherein the second instruction set architecture of the second processor is at least substantially different from the first instruction set architecture of the first processor, or at least substantially similar to the first instruction set architecture of the first processor.

24. The apparatus of claim 22, further comprising:

a broadcast module operable to encode a computer-readable signal-bearing medium with the execution optimization information.

25. The apparatus of claim 22, further comprising:

a broadcast module operable to transmit a computer-readable signal- bearing medium encoded with the execution optimization information.

26. An apparatus comprising:

a receiver module operable to acquire data transparent to software executing on a first processor having a first microarchitecture and corresponding to a runtime execution of a first instruction by the first processor; and

a generator module operable to create an execution optimization information useable in an execution of a second instruction by a second processor having a second microarchitecture.

27. The apparatus of claim 26, wherein the second microarchitecture of the second processor is at least substantially different from the first microarchitecture of the first processor or at least substantially similar to the first microarchitecture of the first processor.

28. A method comprising:

receiving hardware-gathered data corresponding to a runtime execution of a first instruction by a first processor having a first architecture; and

creating an execution optimization information useable in an execution of a second instruction by a second processor having a second architecture.

29. The method of claim 28, wherein the receiving hardware-gathered data corresponding to a runtime execution of a first instruction by a first processor having a first architecture includes

receiving hardware-gathered data corresponding to a runtime execution of a first instruction by a first processor having a first instruction set architecture.

30. The method of claim 28, wherein the receiving hardware-gathered data corresponding to a runtime execution of a first instruction by a first processor having a first architecture includes

receiving hardware-gathered data corresponding to a runtime execution of a first instruction by a first processor having a first microarchitecture.

31. The method of claim 28, wherein the creating an execution optimization information useable in an execution of a second instruction by a second processor having a second architecture includes

creating an execution optimization information useable in an execution of a second instruction by a second processor having a second architecture in response to the received hardware-gathered data.

32. The method of claim 28, wherein the creating an execution optimization information useable in an execution of a second instruction by a second processor having a second architecture includes

creating an execution optimization information useable in an execution of a second instruction by a second processor having a second architecture in response to the received hardware-gathered data.

33. The method of claim 28, wherein the creating an execution optimization information useable in an execution of a second instruction by a second processor having a second architecture includes

creating an execution optimization information useable in an execution of a second instruction by a second processor having a second microarchitecture.

34. The method of claim 28, further comprising:

saving the execution optimization information.

35. The method of claim 28, further comprising:

marketing the execution optimization information.

36. The method of claim 28, further comprising:

facilitating entry of the execution optimization information into a stream of commerce.

37. The method of claim 28, further comprising:

encoding a computer-readable signal-bearing medium with the execution optimization information.

38. The method of claim 37, further comprising:

broadcasting the computer-readable signal-bearing medium encoded with the execution optimization information.

39. An apparatus comprising:

an execution-based optimization profile usable during an execution of a computer program by a second processor having a second architecture and derived by a hardware device utilizing data generated during a runtime execution of the computer program by a first processor having a first architecture; and

a computer-readable medium encoded with the execution-based optimization profile.

40. The apparatus of claim 39, wherein the execution-based optimization profile usable during an execution of a computer program by a second processor having a second architecture and derived by a hardware device utilizing data generated during a runtime execution of the computer program by a first processor having a first architecture includes

an execution-based optimization profile usable during an execution of a computer program by a second processor having a second instruction set architecture and derived by a hardware device utilizing data generated during a runtime execution of the computer program by a first processor having a first instruction set architecture.

41. The apparatus of claim 39, wherein the execution-based optimization profile usable during an execution of a computer program by a second processor having a second architecture and derived by a hardware device utilizing data generated during a runtime execution of the computer program by a first processor having a first architecture includes

an execution-based optimization profile usable during an execution of a computer program by a second processor having a second microarchitecture and derived by a hardware device utilizing data generated during a runtime execution of the computer program by a first processor having a first microarchitecture.

42. The apparatus of claim 39, wherein the computer-readable medium includes a computer storage medium.

43. The apparatus of claim 41, wherein the computer storage medium includes a transportable computer storage medium.

44. The apparatus of claim 41, wherein the computer storage medium includes a portable computer storage medium.

45. The apparatus of claim 39, wherein the computer-readable medium includes a computer-readable communications medium.