Cryptography methods and apparatus

• US 20070050641A1
• Filed: 08/26/2005
• Published: 03/01/2007
• Est. Priority Date: 08/26/2005
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Flynn, William, Shedivy, David
• Granted Patent: US 8,566,607 B2
• Time in Patent Office: Days
• US Class Current: 713/189
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862

Abstract

In a first aspect, a first cryptography method is provided. The first method includes the steps of (1) in response to receiving a request to perform a first operation on data in a first memory cacheline, accessing data associated with the first memory cacheline; (2) performing cryptography on data of the first memory cacheline when necessary; and (3) speculatively accessing data associated with a second memory cacheline based on the first memory cacheline before receiving a request to perform an operation on data in the second memory cacheline. Numerous other aspects are provided.

Claims

1. A cryptography method, comprising:

in response to receiving a request to perform a first operation on data in a first memory cacheline, accessing data associated with the first memory cacheline;

performing cryptography on data of the first memory cacheline when necessary; and

speculatively accessing data associated with a second memory cacheline based on the first memory cacheline before receiving a request to perform an operation on data in the second memory cacheline.

2. The method of claim 1 further comprising:

receiving a request to perform a second operation on data in the second memory cacheline; and

employing the speculatively accessed data to complete the second operation.

3. The method of claim 2 wherein employing the speculatively accessed data to complete the second operation includes reducing a time required to perform the second operation.

4. The method of claim 2 wherein the second operation includes cryptography on data in the second memory cacheline.

5. The method of claim 1 wherein the first and second memory cachelines are successive.

6. The method of claim 1 further comprising, in response to receiving a request to perform a third operation, stopping the speculative access to perform the third operation.

7. The method of claim 1 wherein speculatively accessing data associated with a second memory cacheline includes speculatively accessing data in the second memory cacheline.

8. A cryptography apparatus, comprising:

controller logic, adapted to couple to a processing unit and a memory of a system, and further adapted to;

in response to receiving a request to perform a first operation on data in a first memory cacheline, access data associated with the first memory cacheline;

perform cryptography on data of the first memory cacheline when necessary; and

speculatively access data associated with a second memory cacheline based on the first memory cacheline before receiving a request to perform an operation on data in the second memory cacheline.

9. The apparatus of claim 8 wherein the controller logic is further adapted to:

receive a request to perform a second operation on data in the second memory cacheline; and

employ the speculatively accessed data to complete the second operation.

10. The apparatus of claim 9 wherein the controller logic is further adapted to reduce a time required to perform the second operation.

11. The apparatus of claim 9 wherein the second operation includes cryptography on data in the second memory cacheline.

12. The apparatus of claim 8 wherein the first and second memory cachelines are successive.

13. The apparatus of claim 8 wherein the controller logic is further adapted to, in response to receiving a request to perform a third operation, stop the speculative access to perform the third operation.

14. The apparatus of claim 8 wherein the controller logic is further adapted to speculatively access data in the second memory cacheline.

15. A cryptography system, comprising:

a processing unit;

a memory; and

controller logic, coupled to the processing unit and memory, and adapted to;

in response to receiving a request to perform a first operation on data in a first memory cacheline, access data associated with the first memory cacheline;

perform cryptography on data of the first memory cacheline when necessary; and

speculatively access data associated with a second memory cacheline based on the first memory cacheline before receiving a request to perform an operation on data in the second memory cacheline.

16. The cryptography system of claim 15 wherein the controller logic is further adapted to:

receive a request to perform a second operation on data in the second memory cacheline; and

employ the speculatively accessed data to complete the second operation.

17. The cryptography system of claim 16 wherein the controller logic is further adapted to reduce a time required to perform the second operation.

18. The cryptography system of claim 16 wherein the second operation includes cryptography on data in the second memory cacheline.

19. The cryptography system of claim 15 wherein the first and second cachelines are successive.

20. The cryptography system of claim 15 wherein the controller logic is further adapted to, in response to receiving a request to perform a third operation, stop the speculative access to perform the third operation.