Hardware-error tolerant computing

US 20070050659A1
Filed: 02/28/2006
Published: 03/01/2007
Est. Priority Date: 08/29/2005
Status: Active Grant

First Claim

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1. A computing system comprising:

a processor subsystem having an adjustable operating parameter;

an information store operable to save a sequence of instructions; and

a controller module including;

a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and

a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.

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Abstract

Embodiments include a computing system, a device, and a method. A computing system includes a processor subsystem having an adjustable operating parameter. The computing system also includes an information store operable to save a sequence of instructions. The computing system further includes a controller module. The controller module includes a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem. The controller further includes a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.

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44 Claims

1. A computing system comprising:
- a processor subsystem having an adjustable operating parameter;
  
  an information store operable to save a sequence of instructions; and
  
  a controller module including;
  
  a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem; and
  
  a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
- - 2. The computing system of claim 1, wherein the controller module including a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem further includes:
    - a controller module including a monitor circuit for detecting an incidence of a computational error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.
  - 3. The computing system of claim 1, wherein the controller module including a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem further includes:
    - a controller module including a monitor circuit for detecting an incidence of an execution path synchronization error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.
  - 4. The computing system of claim 1, wherein the controller module including a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem further includes:
    - a controller module including a hardware-implemented monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.
  - 5. The computing system of claim 1, wherein the controller module including a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem further includes:
    - a controller module including a monitor circuit implemented in at least one of hardware, software, firmware, and/or a microengine for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.
  - 6. The computing system of claim 1, wherein the controller module including a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem further includes:
    - a controller module including a monitor circuit implemented in a dynamic implementation verification architecture (DIVA) and for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.
  - 7. The computing system of claim 1, wherein the controller module including a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem further includes:
    - a controller module including a monitor circuit employing a TEATime execution checker algorithm and for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem.
  - 8. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a control circuit implemented in at least one of hardware, software, firmware, and/or a microengine and for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.
  - 9. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a control circuit implemented in software associated with at least one of an operating system and/or a program executable by the processor subsystem and for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.
  - 10. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for at least one of initiating, activating, causing, facilitating, accomplishing, and/or achieving an adjustment of the adjustable operating parameter based upon an error-tolerant performance criterion.
  - 11. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting a voltage of the processor subsystem based upon an error-tolerant performance criterion.
  - 12. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting a frequency of a timing signal employed by the processor subsystem based upon an error-tolerant performance criterion.
  - 13. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting a processor clock based upon an error-tolerant performance criterion.
  - 14. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting the adjustable operating parameter to substantially minimize a time required to successfully complete an execution of the sequence of instructions.
  - 15. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting the adjustable operating parameter in substantial conformity with an error-tolerant performance criterion that corresponds to $0 = \frac{\begin{matrix} Δ time to complete an execution \\ of the sequence of instructions \end{matrix}}{Δ adjustable operating parameter .}$
  - 16. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting the adjustable operating parameter to substantially minimize a time to complete an execution of the sequence of instructions.
  - 17. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting a processor clock frequency to substantially minimize a time to complete an execution of the sequence of instructions.
  - 18. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting a processor clock frequency in substantial conformity with $0 = \frac{\begin{matrix} Δ time to complete an execution \\ of the sequence of instructions \end{matrix}}{Δ processor clock frequency .}$
  - 19. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting a processor clock frequency in substantial conformity with $0 = \frac{\begin{matrix} Δ time to complete an execution \\ of the sequence of instructions \end{matrix}}{Δ processor clock frequency} .$
  - 20. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting a processor clock frequency in substantial conformity with $\pm 0.05 = \frac{\begin{matrix} Δ time to complete an execution \\ of the sequence of instructions \end{matrix}}{Δ processor clock frequency} .$
  - 21. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting a processor clock frequency in substantial conformity with $\pm 0.20 = \frac{\begin{matrix} Δ time to complete an execution \\ of the sequence of instructions \end{matrix}}{Δ processor clock frequency} .$
  - 22. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting a processor voltage to substantially minimize a time to complete an execution of the sequence of instructions.
  - 23. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting a processor clock frequency in substantial conformity with $0 = \frac{\begin{matrix} Δ time to complete an execution \\ of the sequence of instructions \end{matrix}}{Δ processor clock frequency} .$
  - 24. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting a processor clock frequency to substantially minimize an expected time to successfully complete an execution of the sequence of instructions while at least one other adjustable operating parameter remains substantially constant.
  - 25. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant dynamically-derived performance criterion.
  - 26. The computing system of claim 25, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant dynamically-derived performance criterion further includes:
    - a controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant dynamically-derived performance criterion having an objective to substantially minimize an expected time to successfully complete an execution of the sequence of instruction.
  - 27. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting the adjustable operating parameter based upon an empirically-based error-tolerant performance map.
  - 28. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting the adjustable operating parameter based upon a performance criterion embodied in a lookup table.
  - 29. The computing system of claim 28, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon a performance criterion embodied in a lookup table further includes:
    - a controller module including a control circuit for adjusting the adjustable operating parameter based upon a performance criterion embodied in a lookup table and having an objective of substantially minimizing a time to complete an execution of the sequence of instruction.
  - 30. The computing system of claim 1, wherein the controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion further includes:
    - a controller module including a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion corresponding to an incidence of the detected operating-parameter-caused error.
  - 31. The computing system of claim 1, wherein the controller module further includes an error recovery circuit operable to restore an execution of the sequence of program instructions to a checkpoint based upon the detected operating-parameter-caused error.

32. A method implemented in a computerized system, the method comprising:
- detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable operating parameter; and
  
  changing the adjustable processor operating parameter based upon an error-tolerant performance criterion.
- View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
- - 33. The method of claim 32, wherein the detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable operating parameter includes:
    - detecting an incidence of a setup/hold violation corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable operating parameter.
  - 34. The method of claim 32, wherein the detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable operating parameter includes:
    - detecting an incidence of an execution path synchronization error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable operating parameter.
  - 35. The method of claim 32, wherein the detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable operating parameter includes:
    - detecting an incidence of at least one of a single incidence, an incidence frequency, an incidence occurrence rate, an incidence tempo, an incidence pattern, or an incidence prevalence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable operating parameter.
  - 36. The method of claim 32, wherein the changing the adjustable processor operating parameter based upon an error-tolerant performance criterion includes:
    - changing the adjustable processor operating parameter based upon an error-tolerant performance criterion to substantially minimize a time required to successfully complete an execution of the sequence of instructions.
  - 37. The method of claim 36, wherein the changing the adjustable processor operating parameter based upon an error-tolerant performance criterion to substantially minimize a time required to successfully complete an execution of the sequence of instructions includes changing at least one of a voltage of the processor subsystem and/or a processor clock frequency based upon an error-tolerant performance criterion to substantially minimize a time required to successfully complete an execution of the sequence of instructions.
  - 38. The method of claim 36, wherein the changing the adjustable processor operating parameter based upon an error-tolerant performance criterion to substantially minimize a time required to successfully complete an execution of the sequence of instructions includes changing the adjustable processor operating parameter based upon an error-tolerant and dynamically-derived performance criterion having an objective to substantially minimize a time to execute the sequence of instruction by the processor subsystem.
  - 39. The method of claim 32, wherein the changing the adjustable processor operating parameter based upon an error-tolerant performance criterion includes:
    - changing a processor clock frequency in substantial conformity with $0 = \frac{\begin{matrix} Δ time to complete an execution \\ of the sequence of instructions \end{matrix}}{Δ processor clock frequency}$
  - 40. The method of claim 32, wherein the changing the adjustable processor operating parameter based upon an error-tolerant performance criterion includes:
    - changing a processor voltage in substantial conformity with $0 = \frac{\begin{matrix} Δ time to complete an execution \\ of the sequence of instructions \end{matrix}}{Δ processor voltage} .$
  - 41. The method of claim 32, wherein the changing the adjustable processor operating parameter based upon an error-tolerant performance criterion includes:
    - determining that changing the adjustable processor operating parameter is at least substantially likely to decrease a time to complete an execution of the sequence of instructions by the processor and changing the adjustable processor operating parameter based upon an error-tolerant performance criterion.
  - 42. The method of claim 32, further comprising:
    - restoring an execution of the sequence of program instructions to a checkpoint based upon the detected processor-operating-parameter-caused error.

43. A device comprising:
- means for detecting an incidence of a processor-operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by a processor subsystem having an adjustable operating parameter; and
  
  means for changing the adjustable processor operating parameter based upon an error-tolerant performance criterion.
- View Dependent Claims (44)
- - 44. The device of claim 43, further comprising:
    - means for restoring an execution of the sequence of program instructions to a checkpoint based upon the detected processor-operating-parameter-caused error.

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Current Assignee
The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
Original Assignee
Searete LLC (Intellectual Ventures LLC)
Inventors
Ferren, Bran, Tegreene, Clarence, Myhrvold, Nathan, Wood, Lowell, Hillis, W., Mangione-Smith, William

Granted Patent

US 7,493,516 B2
Time in Patent Office

Days
Field of Search
US Class Current

714/1
CPC Class Codes

G06F 11/0721   within a central processing...

G06F 11/0793   Remedial or corrective acti...

G06F 11/1407   Checkpointing the instructi...

Hardware-error tolerant computing

First Claim

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Abstract

82 Citations

44 Claims

Specification

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Hardware-error tolerant computing

First Claim

3 Assignments

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0 Petitions

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Accused Products

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Abstract

82 Citations

44 Claims

Specification

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