Handling processor computational errors

• US 20070050660A1
• Filed: 02/28/2006
• Published: 03/01/2007
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: Searete LLC (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Tegreene, Clarence, Myhrvold, Nathan, Wood, Lowell, Hillis, W., Mangione-Smith, William
• Granted Patent: US 8,375,247 B2
• Time in Patent Office: Days
• US Class Current: 714/1
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1407 Checkpointing the instruction stream

Abstract

Embodiments include a computer processor-error controller, a computerized device, a device, an apparatus, and a method. A computer processor-error controller includes a monitoring circuit operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction. The computer processor-error controller includes an error recovery circuit operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error.

Claims

1. A computer processor-error controller, the controller comprising:

a monitoring circuit operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction; and

an error recovery circuit operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error.

2. The controller of claim 1, wherein the monitoring circuit operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction further includes:

a monitoring circuit implemented in hardware and operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction.

3. The controller of claim 1, wherein the monitoring circuit operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction further includes:

a monitoring circuit implemented in a dynamic implementation verification architecture (DIVA) and operable to detect a setup/hold violation corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction.

4. The controller of claim 1, wherein the monitoring circuit operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction further includes:

a hardware implemented monitoring circuit employing a TEATime execution checker algorithm and operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction.

5. The controller of claim 1, wherein the monitoring circuit operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction further includes:

a hardware implemented monitoring circuit employing another processor operable to execute the second instruction substantially in parallel with the processor, and operable to detect a computational error corresponding to an execution of a second instruction by the processor by correlating an output of the processor with the output of the another processor.

6. The controller of claim 1, wherein the monitoring circuit operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction further includes:

a monitoring circuit operable to detect at least one of a computational error corresponding to a setup/hold violation, a processor clock speed, a processor voltage, a noise spike, a cosmic particle, a soft error, a single event upset failure, an unreliable processor hardware, an incorrectly executed instruction, and/or a electromigration error corresponding to an execution of a second instruction by the processor.

7. The controller of claim 1, wherein the monitoring circuit operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction further includes:

a hardware implemented monitoring circuit operable to detect a computational error corresponding to a setup/hold violation occurring in a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction.

8. The controller of claim 1, wherein the error recovery circuit operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error includes:

an error recovery circuit operable to restore an execution of the sequence of program instructions to a logical state associated with the first instruction in response to the detected computational error.

9. The controller of claim 1, wherein the error recovery circuit operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error includes:

an error recovery circuit implemented in at least one of hardware, software, firmware, and/or a microengine and operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error.

10. The controller of claim 1, wherein the error recovery circuit operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error includes:

an error recovery circuit implemented in software associated with at least one of an operating system or a program executable by the processor and operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error.

11. The controller of claim 1, wherein the error recovery circuit operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error includes:

an error recovery circuit operable to designate the first instruction as a checkpoint and to restore an execution of the sequence of program instructions to the checkpoint in response to the detected computational error.

12. The controller of claim 1, wherein the error recovery circuit operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error includes:

an error recovery circuit operable to designate the first instruction as an instruction separated from the second instruction by a predetermined number of instructions and to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error.

13. The controller of claim 1, wherein the error recovery circuit operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error includes:

an error recovery circuit operable to select the first instruction corresponding to a checkpoint protocol and to rollback an execution of the sequence of program instructions to the selected checkpoint in response to the detected computational error.

14. The controller of claim 1, wherein the controller and the processor are formed on a single chip.

15. The controller of claim 1, further comprising:

a computing system that includes the controller, the processor, and an information store.

16. A computerized device comprising:

a processor operable to execute a sequence of program instructions having a fetch order that includes a first instruction that is fetched before a second instruction; and

a controller that includes;

a hardware-implemented execution verification circuit for detecting a computational error corresponding to an execution of the second instruction by the processor; and

an error recovery circuit for rolling back an execution of the sequence of program instructions to a logical state associated with the first instruction in response to the detected computational error.

17. The computerized device of claim 16, wherein the controller that includes an error recovery circuit for rolling back an execution of the sequence of program instructions to a logical state associated with the first instruction in response to the detected computational error further includes:

a controller that includes an error recovery circuit for at least one of initiating, activating, causing, facilitating, accomplishing, and/or achieving a rollback of an execution of the sequence of program instructions to a logical state associated with the first instruction in response to the detected computational error.

18. The computerized device of claim 16, wherein the controller that includes an error recovery circuit for rolling back an execution of the sequence of program instructions to a logical state associated with the first instruction in response to the detected computational error further includes:

a controller that includes an error recovery circuit implemented in at least one of hardware, software, firmware, and/or microengine for rolling back an execution of the sequence of program instructions to a logical state associated with the first instruction in response to the detected computational error.

19. The computerized device of claim 16, wherein the processor and the controller are formed on a same chip.

20. The computerized device of claim 16, further comprising:

a computerized device that includes the processor, the controller, and an information store.

21. A method comprising:

sensing a computational error corresponding to an execution of a second instruction by a processor operable to execute an instruction sequence having a first instruction that is fetched before the second instruction; and

restoring an execution of the instruction sequence to a logical state associated with the first instruction in response to the sensed computational error.

22. The method of claim 21, wherein the sensing a computational error corresponding to an execution of a second instruction by a processor operable to execute an instruction sequence having a first instruction that is fetched before the second instruction includes:

sensing a computational fault corresponding to an execution of a second instruction by a processor operable to execute an instruction sequence having a first instruction that is fetched before the second instruction.

23. The method of claim 21, wherein the sensing a computational error corresponding to an execution of a second instruction by a processor operable to execute an instruction sequence having a first instruction that is fetched before the second instruction includes:

sensing an execution path synchronization error corresponding to an execution of a second instruction by a processor operable to execute an instruction sequence having a first instruction that is fetched before the second instruction.

24. The method of claim 21, wherein the sensing a computational error corresponding to an execution of a second instruction by a processor operable to execute an instruction sequence having a first instruction that is fetched before the second instruction includes:

sensing an error correlating to a voltage applied to a processor and that corresponds to an execution of a second instruction by the processor operable to execute an instruction sequence having a first instruction that is fetched before the second instruction.

25. The method of claim 21, wherein the sensing a computational error corresponding to an execution of a second instruction by a processor operable to execute an instruction sequence having a first instruction that is fetched before the second instruction includes:

sensing an error correlating to a processor temperature and corresponding to an execution of a second instruction by a processor operable to execute an instruction sequence having a first instruction that is fetched before the second instruction.

26. The method of claim 21, wherein the sensing a computational error corresponding to an execution of a second instruction by a processor operable to execute an instruction sequence having a first instruction that is fetched before the second instruction includes:

sensing at least one of a computational error correlating to a processor clock speed, a processor voltage, a noise spike, a cosmic particle, a soft error, an unreliable hardware, an incorrectly executed instruction, and/or an electromigration that corresponds to an execution of a second instruction by a processor operable to execute an instruction sequence having a first instruction that is fetched before the second instruction.

27. The method of claim 21, wherein the restoring an execution of the instruction sequence to a logical state associated with the first instruction in response to the sensed computational error includes:

rolling back an execution of the instruction sequence to a checkpoint corresponding to a logical state associated with the execution of the first instruction in response to the sensed computational error.

28. The method of claim 21, wherein the restoring an execution of the instruction sequence to a logical state associated with the first instruction in response to the sensed computational error includes:

restoring an execution of the instruction sequence to a logical state associated with the first instruction determined by a checkpoint protocol and in response to the sensed computational error.

29. A device comprising:

means for sensing a computational error corresponding to an execution of a second instruction by a processor operable to execute an instruction sequence having a first instruction that is fetched before the second instruction; and

means for restoring an execution of the instruction sequence to the first instruction in response to the sensed computational error.