Adjusting a processor operating parameter based on a performance criterion

• US 20070050661A1
• Filed: 02/28/2006
• Published: 03/01/2007
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Tegreene, Clarence, Myhrvold, Nathan, Wood, Lowell, Hillis, W., Mangione-Smith, William
• Granted Patent: US 7,607,042 B2
• Time in Patent Office: Days
• US Class Current: 714/1
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1407 Checkpointing the instruction stream

Abstract

Embodiments include a controller apparatus, a computerized apparatus, a device, an apparatus, and a method. A controller-apparatus includes a monitoring circuit for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter. The controller apparatus also includes a recovery circuit for rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error. The controller apparatus further includes a control circuit for adjusting the adjustable operating parameter in response to a performance criterion.

Claims

1. A controller apparatus comprising:

a monitoring circuit for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter;

a recovery circuit for rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error; and

a control circuit for adjusting the adjustable operating parameter in response to a performance criterion.

2. The controller apparatus of claim 1, wherein the monitoring circuit for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter includes:

a hardware-implemented monitoring circuit for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter.

3. The controller apparatus of claim 1, wherein the monitoring circuit for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter includes:

a monitoring circuit implemented in at least one of hardware, software, firmware, and/or a microengine for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter.

4. The controller apparatus of claim 1, wherein the monitoring circuit for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter includes:

a monitoring circuit implemented in a dynamic implementation verification architecture (DIVA) and for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter.

5. The controller apparatus of claim 1, wherein the monitoring circuit for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter includes:

a monitoring circuit employing a TEATime execution checker algorithm and for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter.

6. The controller apparatus of claim 1, wherein the recovery circuit for rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error includes:

a recovery circuit implemented in at least one of hardware, software, firmware, and/or a microengine and for rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error.

7. The controller apparatus of claim 1, wherein the recovery circuit for rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error includes:

a recovery circuit implemented in software associated with at least one of an operating system or a program executable by the processor subsystem and for rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error.

8. The controller apparatus of claim 1, wherein the recovery circuit for rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error includes:

a recovery circuit for at least one of initiating, activating, causing, facilitating, accomplishing, and/or achieving a re-execution of the instruction by the processor subsystem by rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error.

9. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting the adjustable operating parameter in response to a performance criterion corresponding to an incidence of the detected computational error.

10. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit implemented in at least one of hardware, software, firmware, and/or a microengine and for adjusting the adjustable operating parameter in response to a performance criterion.

11. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion:

a control circuit implemented in software associated with at least one of an operating system and/or a program executable by the processor subsystem and for adjusting the adjustable operating parameter in response to a performance criterion.

12. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting the adjustable operating parameter in response to a performance criterion corresponding to an incidence of a detected processor subsystem computational error.

13. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for at least one of initiating, activating, causing, facilitating, accomplishing, and/or achieving an adjustment of the adjustable operating parameter in response to a performance criterion.

14. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting a voltage of the processor subsystem in response to a performance criterion.

15. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance includes:

a control circuit for adjusting a processor subsystem in response to a performance criterion corresponding to an incidence of the detected computational error.

16. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting a frequency of a timing signal employed by the processor subsystem in response to a performance criterion.

17. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting a processor subsystem clock in response to a performance criterion corresponding to an incidence of the detected computational error.

18. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting the adjustable operating parameter in response to a performance criterion corresponding to at least one of a single incidence of the detected computational error, an incidence frequency of the detected computational error, an incidence occurrence rate of the detected computational error, an incidence tempo of the detected computational error, an incidence pattern of the detected computational error, or an incidence prevalence of the detected computational error.

19. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting the adjustable operating parameter based on a performance criterion substantially minimizing time required to successfully complete an execution of the sequence of instructions.

20. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting the adjustable operating parameter in a substantial conformity with a performance criterion corresponding to

$0=\frac{\mathrm{\Delta <br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{time}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{to}<br><br>\text{\hspace{1em}<br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{complete}<br><br>\text{\hspace{1em}<br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{an}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{execution}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{of}<br><br>\text{\hspace{1em}<br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{the}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{sequence}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{of}<br><br>\text{\hspace{1em}<br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{instructions}}{\mathrm{\Delta <br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{adjustable}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{operating}<br><br>\text{\hspace{1em}<br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{parameter}}.$

21. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting the adjustable operating parameter in response to a performance criterion corresponding to a substantial minimization of time to complete an execution of the sequence of instructions.

22. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting a processor subsystem clock signal frequency based upon a performance criterion corresponding to a substantial minimization of time to complete an execution of the sequence of instructions.

23. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting a processor subsystem clock signal frequency in substantial conformity with a performance criterion corresponding to

$0=\frac{\mathrm{\Delta <br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{time}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{to}<br><br>\text{\hspace{1em}<br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{complete}<br><br>\text{\hspace{1em}<br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{an}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{execution}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{of}<br><br>\text{\hspace{1em}<br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{the}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{sequence}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{of}<br><br>\text{\hspace{1em}<br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{instructions}}{\mathrm{\Delta <br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{processor}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{subsystem}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{clock}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{frequency}}.$

24. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting a processor subsystem voltage in response to a performance criterion corresponding to a substantial minimization of time to execute the sequence of instructions.

25. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting a processor subsystem voltage in substantial conformity with a performance criterion corresponding to

$0=\frac{\mathrm{\Delta <br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{time}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{to}<br><br>\text{\hspace{1em}<br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{complete}<br><br>\text{\hspace{1em}<br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{an}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{execution}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{of}<br><br>\text{\hspace{1em}<br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{the}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{sequence}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{of}<br><br>\text{\hspace{1em}<br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{instructions}}{\mathrm{\Delta <br><br>}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{processor}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{subsystem}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{voltage}}.$

26. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting the adjustable operating parameter based upon a performance criterion substantially minimizing an expected time to successfully complete an execution of the sequence of instructions while at least one other adjustable operating parameter remains substantially constant.

27. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting the adjustable operating parameter based upon a performance criterion and a dynamically-derived incidence of the detected computational error.

28. The controller apparatus of claim 27, wherein the dynamically-derived performance criterion includes a dynamically-derived performance criterion having an objective to substantially minimize an expected time to successfully complete an execution of the sequence of instructions.

29. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting the adjustable operating parameter based upon a performance map and an empirically-based incidence of the detected computational error.

30. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance includes:

a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion corresponding to an incidence of the detected computational error.

31. The controller apparatus of claim 1, wherein the control circuit for adjusting the adjustable operating parameter in response to a performance criterion includes:

a control circuit for adjusting the adjustable operating parameter in response to a performance criterion embodied in a lookup table and an incidence of the detected computational error.

32. The controller apparatus of claim 31, wherein the performance criterion embodied in the lookup table includes a performance criterion embodied in a lookup table having an objective to substantially minimize an expected time to execute the sequence of instructions.

33. A computerized apparatus comprising:

a processor subsystem having an adjustable operating parameter and operable to execute a sequence of instructions;

a sensing module operable to detect an operating-parameter-induced error in an execution of an instruction of the sequence of instructions;

a recovery module operable to rollback an execution of the sequence of instructions to a checkpoint in response to the detected operating-parameter-induced error; and

a control module operable to adjust the adjustable operating parameter in response to a performance criterion corresponding to an incidence of the detected operating-parameter-induced error.

34. The computerized apparatus of claim 33, wherein the sensing module operable to detect an operating-parameter-induced error in an execution of an instruction of the sequence of instructions includes:

a sensing module operable to detect a computational error in an execution of an instruction of the sequence of instructions.

35. The computerized apparatus of claim 33, wherein the sensing module operable to detect an operating-parameter-induced error in an execution of an instruction of the sequence of instructions includes:

a sensing module operable to detect an execution path synchronization error in an execution of an instruction of the sequence of instructions.

36. The computerized apparatus of claim 33, wherein the sensing module operable to detect an operating-parameter-induced error in an execution of an instruction of the sequence of instructions includes:

a sensing module operable to detect a clock-induced error in an execution of an instruction of the sequence of instructions.

37. The computerized apparatus of claim 33, wherein the sensing module operable to detect an operating-parameter-induced error in an execution of an instruction of the sequence of instructions includes:

a sensing module operable to detect a processor voltage induced error in an execution of an instruction of the sequence of instructions.

38. The computerized apparatus of claim 33, wherein the sensing module operable to detect an operating-parameter-induced error in an execution of an instruction of the sequence of instructions includes:

a sensing module implemented in hardware and operable to detect an operating-parameter-induced error in an execution of an instruction of the sequence of instructions.

39. The computerized apparatus of claim 33, wherein the recovery module operable to rollback an execution of the sequence of instructions to a checkpoint in response to the detected operating-parameter-induced error includes:

a recovery module implemented in at least one of hardware, software, firmware, and/or a microengine and operable to rollback an execution of the sequence of instructions to a checkpoint in response to the detected operating-parameter-induced error.

40. The computerized apparatus of claim 33, wherein the control module operable to adjust the adjustable operating parameter in response to a performance criterion corresponding to an incidence of the detected operating-parameter-induced error includes:

a control module implemented in at least one of hardware, software, firmware, and/or a microengine and operable to adjust the adjustable operating parameter in response to a performance criterion corresponding to an incidence of the detected operating-parameter-induced error.

41. The computerized apparatus of claim 33, wherein the control module operable to adjust the adjustable operating parameter in response to a performance criterion corresponding to an incidence of the detected operating-parameter-induced error includes:

a control module operable to adjust the adjustable operating parameter in response to an error-tolerant performance criterion corresponding to an incidence of the detected operating-parameter-induced error.

42. The computerized apparatus of claim 33, wherein the processor subsystem and at least one of the sensing module, the recovery module, and/or the control module are formed on a same chip.

43. A method comprising:

detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor having an adjustable operating parameter;

rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error; and

changing the adjustable processor operating parameter in response to a performance criterion corresponding to an incidence of the detected computational error.

44. The method of claim 43, wherein the changing the adjustable processor operating parameter in response to a performance criterion corresponding to an incidence of the detected computational error includes:

determining that changing the adjustable processor operating parameter is at least substantially likely to decrease an expected time to successfully complete an execution of the sequence of instructions, and appropriately changing the adjustable processor operating parameter in response to a performance criterion corresponding to an incidence of the detected computational error.

45. The method of claim 43, wherein the changing the adjustable processor operating parameter in response to a performance criterion corresponding to an incidence of the detected computational error includes:

changing the adjustable processor operating parameter in response to a performance criterion substantially minimizing a time to complete an execution of the sequence of instructions.

46. The method of claim 43, wherein the changing the adjustable processor operating parameter in response to a performance criterion corresponding to an incidence of the detected computational error includes:

changing a voltage supplied to the processor in response to a performance criterion corresponding to an incidence of the detected computational error.

47. The method of claim 43, wherein the changing the adjustable processor operating parameter in response to a performance criterion corresponding to an incidence of the detected computational error includes:

changing the adjustable processor operating parameter in response to an error-tolerant performance criterion corresponding to an incidence of the detected computational error.

48. A device comprising:

means for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor having an adjustable operating parameter;

means for rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error; and

means for changing the adjustable processor operating parameter in response to a performance criterion corresponding to an incidence of the detected computational error.