TFT array substrate of TFT LCD having large storage capcitor and method for manufacturing same

• US 20070051954A1
• Filed: 09/05/2006
• Published: 03/08/2007
• Est. Priority Date: 09/05/2005
• Status: Abandoned Application

• Current Assignee: InnoLux Corporation
• Original Assignee: Innolux Display Corporation (InnoLux Corporation)
• Inventors: Yan, Shuo-Ting
• Application Number:
  US11/515,578
• Publication Number:
  US 20070051954A1
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

An exemplary thin film transistor (TFT) array substrate includes a glass substrate (430), a semiconductor layer (440) formed on the glass substrate, a gate insulating layer (407) formed on the semiconductor layer, and a plurality of gate electrodes (410) and common electrodes (411) formed on the gate insulating layer. A portion of the gate insulating layer corresponding to the common electrode includes introduced impurities to enhance a dielectric constant thereof. A method for manufacturing the TFT array substrate is also provided.

Claims

1. A thin film transistor (TFT) array substrate, comprising:

a glass substrate;

a semiconductor layer formed on the glass substrate;

a gate insulating layer formed on the semiconductor layer; and

a plurality of gate electrodes and common electrodes formed on the gate insulating layer;

wherein a portion of the gate insulating layer corresponding to the common electrode comprises introduced impurities to enhance a dielectric constant thereof.

2. The TFT array substrate as claimed in claim 1, wherein said portion of the gate insulating layer is covered by the common electrode.

3. The TFT array substrate as claimed in claim 1, wherein the gate insulating layer is made of silicon oxide.

4. The TFT array substrate as claimed in claim 3, wherein the impurities comprise nitrogen ions.

5. The TFT array substrate as claimed in claim 3, wherein the impurities are selected from the group consisting of carbon, fluorine, silicon, and germanium oxide.

6. The TFT array substrate as claimed in claim 3, wherein the impurities are selected from the group consisting of chlorine, bromine, sulfur, iodine, hydrogen, phosphorus, tellurium, boron, and arsenic.

7. The TFT array substrate as claimed in claim 1, wherein the gate electrodes and the common electrodes are made of metal material such as aluminum or copper.

8. The TFT array substrate as claimed in claim 7, wherein the gate electrodes and the common electrodes are made of aluminum or copper.

9. The TFT array substrate as claimed in claim 1, wherein the semiconductor comprises a p-type semiconductor layer and an n⁺-type semiconductor layer.

10. The TFT array substrate as claimed in claim 1, wherein a dielectric constant of the portion of the gate insulating layer doped with the impurities is in the range from 3.9 to 7.9.

12. The method for manufacturing a TFT array substrate as claimed in claim 10, wherein the common electrodes cover the portions of the insulating layer doped with the impurities.

13. The method for manufacturing a TFT array substrate as claimed in claim 10, wherein the impurities are introduced into the portions of the insulating layer by a chemical vapor deposition (CVD) process.

14. The method for manufacturing a TFT array substrate as claimed in claim 13, wherein the impurities are introduced into the portions of the insulating layer by a plasma CVD process, a low pressure CVD process, or a normal pressure CVD process.

15. The method for manufacturing a TFT array substrate as claimed in claim 10, wherein the impurities are introduced into the portions of the insulating layer by an ion implantation process.

16. The method for manufacturing a TFT array substrate as claimed in claim 10, wherein the impurities are selected from the group consisting of nitrogen, carbon, fluorine, silicon, and germanium oxide.

17. The method for manufacturing a TFT array substrate as claimed in claim 10, wherein the impurities are selected from the group consisting of chlorine, bromine, sulfur, iodine, hydrogen, phosphorus, tellurium, boron, and arsenic.

18. The method for manufacturing a TFT array substrate as claimed in claim 10, wherein the gate electrodes and the common electrodes are made of metal material.

19. The method for manufacturing a TFT array substrate as claimed in claim 18, wherein the gate electrodes and the common electrodes are made of aluminum or copper.

20. The method for manufacturing a TFT array substrate as claimed in claim 10, wherein a dielectric constant of the portion of the gate insulating layer doped with the impurities is in the range from 3.9 to 7.9.

11. A method for manufacturing a thin film transistor (TFT) array substrate, comprising the steps of:

forming a semiconductor layer over a glass substrate;

forming an insulating layer on the semiconductor layer;

introducing impurities into a plurality of portions of the insulating layer; and

forming a plurality of gate electrodes and a plurality of common electrodes on the insulating layer;

wherein the portions of the insulating layer corresponding to the common electrodes are doped with impurities to enhance a dielectric constant thereof.