Dense non-volatile memory array and method of fabrication
First Claim
Patent Images
1. A non-volatile memory array comprising:
- word lines; and
bit lines generally perpendicular to said word lines, wherein a pitch between two neighboring word lines is less than 2 F.
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Abstract
A non-volatile memory array includes a multiplicity of memory cells, each of whose area is less than 4 F2 per cell (where F is a minimum feature size), and periphery elements to control the memory cells. The present invention also includes a non-volatile memory array which includes word lines and bit lines generally perpendicular to the word lines, with a word line pitch of less than 2 F. In one embodiment, the word lines are made of polysilicon spacers.
108 Citations
24 Claims
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1. A non-volatile memory array comprising:
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word lines; and
bit lines generally perpendicular to said word lines, wherein a pitch between two neighboring word lines is less than 2 F. - View Dependent Claims (2, 3, 6, 7, 8, 12, 13, 14)
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4. A non-volatile memory chip comprising:
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an array of memory cells each of whose area is less than 4 F2 per cell, wherein F is a minimum feature size; and
periphery elements to control said memory cells. - View Dependent Claims (5, 9, 10, 11, 15, 16)
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17. A non-volatile memory array comprising:
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polysilicon spacer word lines; and
bit lines generally perpendicular to said word lines. - View Dependent Claims (18, 19, 20, 21)
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22. A method for word-line patterning of a non-volatile memory array, the method comprising:
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generating word line retaining walls; and
generating polysilion spacer word lines to the sides of said retaining walls. - View Dependent Claims (23, 24)
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Specification