Semiconductor device and manufacturing method therefor

• US 20070052017A1
• Filed: 04/27/2006
• Published: 03/08/2007
• Est. Priority Date: 04/27/2005
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Okanishi, Masatomi
• Granted Patent: US 7,825,457 B2
• Time in Patent Office: Days
• US Class Current: 257/336
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line(30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a high concentration diffusion region formed in the semiconductor substrate;

a first low concentration diffusion region formed under the high concentration diffusion region and having a lower concentration than the high concentration diffusion region; and

a bit line including the high concentration diffusion region and the first low concentration diffusion region and including a source region and a drain region.

2. The semiconductor device as claimed in claim 1, further comprising pocket ion implantation regions formed at both sides of the high concentration diffusion region and included in the bit line.

3. The semiconductor device as claimed in claim 1, wherein a width of the first low concentration diffusion region is narrower than that of the high concentration diffusion region.

4. The semiconductor device as claimed in claim 1, wherein a width of the first low concentration diffusion region is substantially equal to that of the high concentration diffusion region.

5. The semiconductor device as claimed in claim 1, further comprising second low concentration diffusion regions formed at both sides of the high concentration diffusion region and having a lower concentration than the high concentration diffusion region and included in the bit line.

6. The semiconductor device as claimed in claim 1, further comprising:

an ONO film provided on the semiconductor substrate; and

a word line provided on the ONO film and including a gate electrode.

7. The semiconductor device as claimed in claim 6, wherein the ONO film has multiple charge storage regions under the gate electrode and between bit lines.

8. A method of fabricating a semiconductor device comprising:

forming a high concentration diffusion region in a semiconductor substrate, the high concentration diffusion region being included in a source region and a drain region; and

forming a first low concentration diffusion region under the high concentration diffusion region, the first low concentration diffusion region having a lower concentration than the high concentration diffusion region and included in the bit line.

9. The method as claimed in claim 8, further comprising forming a mask layer over the semiconductor substrate, wherein each of the step of forming the high concentration diffusion region and the step of forming of the first low concentration diffusion region includes a step of implanting ions in the semiconductor substrate by using the mask layer.

10. The method as claimed in claim 9, wherein an opening in the mask layer expanded by ion implantation, the step of forming the high concentration diffusion region is performed after the step of forming the first low concentration diffusion region.

11. The method as claimed in claim 10, wherein the mask layer includes a photo resist layer.

12. The method as claimed in claim 9, wherein the mask layer includes a metal or insulator.

13. The method as claimed in claim 8 further comprising;

forming sidewalls at both sides of the mask layer, wherein;

the step of forming the high concentration diffusion region implants ions in the semiconductor substrate by using the mask layer as a mask for ion implantation; and

the step of forming the first low concentration diffusion region implants ions in the substrate by using the mask layer and the sidewalls as a mask for ion implantation.

14. The method as claimed in claim 9, further comprising forming pocket ion implantation regions, at both sides of the high concentration diffusion region, by using the mask layer as a mask for pocket ion implantation, the pocket ion implantation regions included in the bit line.

15. The method as claimed in claim 8, further comprising forming second low concentration diffusion regions at both sides of the high concentration diffusion region, the second low concentration diffusion regions having a lower concentration than the high concentration diffusion region and included in the bit line.

16. The method as claimed in claim 8 further comprising:

forming an ONO film on the semiconductor substrate; and

forming a wide line on the ONO film, the wide line including a gate electrode.