SCHMITT TRIGGER WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION

• US 20070052465A1
• Filed: 09/06/2006
• Published: 03/08/2007
• Est. Priority Date: 09/08/2005
• Status: Abandoned Application

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Wu, Ho-Chun
• Application Number:
  US11/470,257
• Publication Number:
  US 20070052465A1
• Time in Patent Office: Days
• US Class Current: 327/206
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

An Schmitt trigger with electrostatic discharge protection includes a first PMOS, a second PMOS, a first NMOS, and a second NMOS, which are connected in series and each of which has a gate coupled to an input terminal. The drain of the second PMOS is coupled to an output terminal. The source of the first PMOS is coupled to a first voltage. The source of the second NMOS is coupled to a second voltage. The Schmitt trigger further includes a third PMOS, which has a gate coupled to the output terminal, a source coupled to the drain of the first PMOS, and a drain coupled to the second voltage through a poly-silicon resistor; and a third NMOS which has a gate coupled to the output terminal, a source coupled to the source of the first NMOS, and a drain coupled to the first voltage through a poly-silicon resistor.

Claims

1. An Schmitt trigger with electrostatic discharge protection comprising:

a first PMOS transistor having a gate coupled to an input terminal of the Schmitt trigger, a source coupled to a first voltage, and a drain;

a second PMOS transistor having a gate coupled to the input terminal of the Schmitt trigger, a source coupled to the drain of the first PMOS transistor, and a drain coupled to an output terminal of the Schmitt trigger;

a first NMOS transistor having a gate coupled to the input terminal of the Schmitt trigger, a drain coupled to the drain of the second PMOS transistor, and a source;

a second NMOS transistor having a gate coupled to the input terminal of the Schmitt trigger, a drain coupled to the source of the first NMOS transistor, and a source coupled to a second voltage;

a third PMOS transistor having a gate coupled to the output terminal of the Schmitt trigger, a source coupled to the drain of the first PMOS transistor, and a drain coupled to the second voltage through a poly-silicon resistor; and

a third NMOS transistor having a gate coupled to the output terminal of the Schmitt trigger, a source coupled to the source of the first NMOS transistor, and a drain coupled to the first voltage through a poly-silicon resistor.

2. The Schmitt trigger of claim 1 is manufactured by 0.35-μ

m process or a more advanced process.

3. The Schmitt trigger of claim 1, wherein the first voltage is a VDD voltage and the second voltage is a VSS voltage.

4. An Schmitt trigger with electrostatic discharge protection comprising:

a plurality of cascaded transistors comprising;

a first transistor having a gate coupled to an input terminal of the Schmitt trigger, and a source coupled to a first voltage; and

a second transistor having a gate coupled to the input terminal of the Schmitt trigger, and a source coupled to a second voltage;

a third transistor having a source coupled to a drain of the first transistor, and a drain coupled to the second voltage through a first poly-silicon resistor; and

a fourth transistor having a source coupled to a drain of the second transistor, and a drain coupled to the first voltage through a second poly-silicon resistor.

5. The Schmitt trigger of claim 4, wherein the first voltage is a VDD voltage and the second voltage is a VSS voltage.

6. The Schmitt trigger of claim 4, wherein the first and third transistors are PMOS transistors while the second and fourth transistors are NMOS transistors.

7. The Schmitt trigger of claim 4 is manufactured by 0.35-μ

m process or a more advanced process.

8. An Schmitt trigger with electrostatic discharge protection comprising:

a first PMOS transistor having a gate coupled to an input terminal of the Schmitt trigger, a source coupled to a first voltage and a drain;

a second PMOS transistor having a gate coupled to the input terminal of the Schmitt trigger, a source coupled to the drain of the first PMOS transistor and a drain coupled to an output terminal of the Schmitt trigger;

a first NMOS transistor having a gate coupled to the input terminal of the Schmitt trigger, a drain coupled to the drain of the second PMOS transistor and a source;

a second NMOS transistor having a gate coupled to the input terminal of the Schmitt trigger, a drain coupled to the source of the first NMOS transistor and a source coupled to a second voltage;

a third PMOS transistor having a gate coupled to the output terminal of the Schmitt trigger and a source coupled to the drain of the first PMOS transistor;

a third NMOS transistor having a gate coupled to the output terminal of the Schmitt trigger and a source coupled to the source of the first NMOS transistor;

a first impedance unit coupled to a drain of the third PMOS transistor and the second voltage; and

a second impedance unit coupled to a drain of the third NMOS transistor and the first voltage;

wherein the first and the second impedance units are formed with passive devices.

9. The Schmitt trigger of claim 8 is manufactured by 0.35-μ

m process or a more advanced process.

10. The Schmitt trigger of claim 8, wherein the first voltage is a VDD voltage and the second voltage is a VSS voltage.

11. The Schmitt trigger of claim 8, wherein the first and the second impedance units are respectively composed of a poly-silicon resistor.

12. The Schmitt trigger of claim 8, wherein the first and the second impedance units are respectively composed of a metal resistor.

13. The Schmitt trigger of claim 8, wherein the first and the second impedance units are respectively composed of a diffusion resistor.

14. The Schmitt trigger of claim 8, wherein the first and the second impedance units are respectively composed of a well resistor.