Apparatus and method to achieve a constant sample rate for multiplexed signals with frame boundaries

• US 20070053380A1
• Filed: 06/29/2006
• Published: 03/08/2007
• Est. Priority Date: 06/29/2005
• Status: Active Grant

• Current Assignee: Winnov, L.P.
• Original Assignee: Winnov, L.P.
• Inventors: Graham, Harry
• Granted Patent: US 8,374,203 B2
• Time in Patent Office: Days
• US Class Current: 370/466
• CPC Class Codes: H04J 3/16 in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted H04J3/17, H04J3/24 take precedence
• CPC Class Codes: H04N 7/01 Conversion of standards , e.g. involving analogue television standards or digital television standards processed at pixel level

Abstract

Given a hardware platform capable of capturing framed data in a multiplexed fashion from multiple sources, a method and apparatus are shown for providing a constant frame rate for each logical stream.

Claims

1. A method of multiplexing source signals comprising:

receiving a first signal having a first frame rate;

receiving a second signal having a second frame rate;

determining a standard frame rate;

modifying said first signal to comply with said standard frame rate;

modifying said second signal to comply with said standard frame rate; and

combining the first modified signal and the second modified signal such that the first modified signal and the second modified signal are dissociable.

2. A method of achieving frame rates for signals, comprising the steps of:

providing one or more input source streams, each input source stream comprising first framed data, and each input source stream having an associated nominal frame rate;

specifying one or more logical streams, each logical stream comprising second framed data, and each logical stream having an associated specified frame rate;

determining a case of operation;

determining a source sequence length;

determining a source sequence list, wherein the source sequence list has a length and wherein the length of the source sequence list is responsive to the source sequence length; and

selecting input source streams in a sequence, wherein the sequence is responsive to the source sequence list.

3. The method of claim 2, further comprising the step of

determining an efficiency of a system receiving the one or more input source streams;

4. The method of claim 3, wherein

the step of determining the case of operation is responsive to the determined efficiency.

5. The method of claim 3, wherein

the step of determining the source sequence length is responsive to the determined efficiency.

6. The method of claim 3, wherein

the step of determining the source sequence list is responsive to the determined efficiency.

7. The method of claim 2, further comprising the steps of:

determining one or more demands for input resources, wherein each demand is associated with one of the one or more logical streams; and

determining an aggregate demand for input resources.

8. The method of claim 7, further comprising the step of derating the one or more demands for input resources, responsive to the aggregate demand for input resources.

9. The method of claim 7, further comprising the steps of:

specifying a skip process; and

determining a demand for input resources associated with the skip process.

10. A system for achieving frame rates for signals, comprising:

one or more input source streams, each input source stream comprising first framed data, and each input source stream having an associated nominal frame rate;

one or more logical streams, each logical stream comprising second framed data, and each logical stream having an associated specified frame rate;

a source sequence list; and

a multiplexer adapted to receive said one or more input source streams, wherein the multiplexer selectively routes said one or more input source streams, responsive to the source sequence list.

11. The system of claim 10 further comprising

a shared resources adapted to receive one or more selectively routed input source streams from said multiplexer.

12. The system of claim 10 further comprising

a demultiplexer adapted to supply second framed data to said one or more logical streams.

13. The system of claim 10 further comprising

a phase accumulator corresponding to one of the one or more input source streams.

14. The system of claim 10 further comprising

a phase accumulator corresponding to a skip process.

15. The system of claim 10 further comprising

a computer system.

16. The system of claim 15 wherein

the computer system is adapted to run a specified operating system.

17. The system of claim 16 wherein

the computer system is adapted to support a specified driver architecture.