Clock transmission apparatus for network synchronization between systems

• US 20070053474A1
• Filed: 05/13/2004
• Published: 03/08/2007
• Est. Priority Date: 05/13/2003
• Status: Active Grant

• Current Assignee: KT Corporation
• Original Assignee: Hyundai Syscomm, Inc. (Hyundai Motor Group)
• Inventors: Kim, Seung
• Granted Patent: US 7,499,512 B2
• Time in Patent Office: Days
• US Class Current: 375/356
• CPC Class Codes: H04J 3/0638 Clock or time synchronisation among nodes; Internode synchronisation synchronization for ring networks H04L12/422; data switching networks with synchronous transmission H04L12/43
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 69/28 Timers or timing mechanisms used in protocols
• CPC Class Codes: H04L 7/044 using a single bit, e.g. start stop bit
• CPC Class Codes: H04L 7/08 the synchronisation signals recurring cyclically

Abstract

The present invention discloses a clock transmission apparatus for network synchronization between systems wherein a main unit generates a even-second (PP2S) pulse and transmits it to a remote unit and the remote unit uses the received PP2S to generate a system clock and a 10 MHz clock, whereby network synchronization is accomplished between two systems (the main unit and the remote unit). The main unit generates a reference clock, multiplexes the reference clock in a predetermined period to generate an even-second network synchronization clock, and then sends the even-second network synchronization clock to the remote unit using an UTP. Further, the remote unit generates a reference clock and a system clock based on the even-second network synchronization clock received through the UTP. Network synchronization can be maintained between two systems using a cheap UTP (Unshielded Twisted Pair) without using a GPS system (an apparatus for maintaining network synchronization of a high accuracy between the two systems) and an expensive transmission line (an optical cable or a coaxial cable).

Claims

1. A clock transmission apparatus for network synchronization between systems, comprising:

a main unit that generates a reference clock, frequency-divides the reference clock by a predetermined period to generate an even-second network synchronization clock, and then send out the even-second network synchronization clock via a Unshielded Twisted Pair (UTP); and

a remote unit that receives the even-second network synchronization clock from the main unit via the UTP and generates a reference clock and a system clock based on the received even-second network synchronization clock for application to a system.

2. The clock transmission apparatus as claimed in claim 1, wherein the main unit comprises:

a processor for calculating a digital value to output an accurate reference clock and generating a digital signal corresponding to the digital value;

a digital/analog converter for converting the digital signal applied thereto from the processor into an analog signal;

an oscillator for generating an oscillating clock to correspond to the analog signal applied thereto from the digital/analog converter; and

a frequency divider for dividing the frequency of the oscillating clock applied thereto from the oscillator by a predetermined period to generate an even-second network synchronization clock (PP2S) and transmits the generated PP2S to the remote unit through the UTP.

3. The clock transmission apparatus as claimed in claim 1, wherein the remote unit comprises:

a receiving clock synchronizer for receiving the even-second network synchronization clock from the frequency divider of the main unit through the UTP and generating an even-second pulse synchronized to the received network synchronization clock;

an oscillator adapted to be oscillated in response to the even-second pulse applied thereto from the receiving clock synchronizer to generate a reference clock (10 MHz) for application to the system;

a phase-locked loop for detecting a phase difference between the even-second pulse applied thereto from the receiving clock synchronizer and a feedbacked system clock and generating a controlled voltage corresponding to the detected phase difference; and

a voltage-controlled oscillator for correcting a system clock to be outputted using the controlled voltage which is outputted from the phase-locked loop, and applying an accurate system clock (19.6608 MHz) to the system.