Multi-chip stack structure

• US 20070054439A1
• Filed: 07/12/2006
• Published: 03/08/2007
• Est. Priority Date: 07/14/2005
• Status: Abandoned Application

• Current Assignee: Siliconware Precision Industries Co., Ltd. (ASE Technology Holding Co., Ltd.)
• Original Assignee: Siliconware Precision Industries Co., Ltd. (ASE Technology Holding Co., Ltd.)
• Inventors: Yang, Ke
• Application Number:
  US11/485,722
• Publication Number:
  US 20070054439A1
• Time in Patent Office: Days
• US Class Current: 438/127
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/78 Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip

Abstract

A multi-chip stack structure includes at least one first chip having an active surface and an opposed non-active surface, wherein the active surface is formed with a plurality of connecting pads thereon; a plurality of electrical contacts formed around the first chip; an insulating layer formed on the first chip and the electrical contacts, wherein the insulating layer is formed with a plurality of openings for exposing the connecting pads and the electrical contacts; a plurality of redistributed circuit layers formed on the insulating layer, for electrically connecting the connecting pads of the first chip to the electrical contacts; at least one second chip mounted on the redistributed circuit layers and electrically connected to the redistributed circuit layers by a flip-chip or wire-bonding process; and an encapsulant formed on the second chip, the insulating layer and the redistributed circuit layers, with the electrical contacts being exposed from the encapsulant.

Claims

1. A multi-chip stack structure comprising:

at least one first chip having an active surface and an opposed non-active surface, wherein the active surface is formed with a plurality of connecting pads thereon;

a plurality of electrical contacts formed around the first chip;

an insulating layer formed on the first chip and the electrical contacts, wherein the insulating layer is formed with a plurality of openings for exposing the connecting pads of the first chip and the electrical contacts;

a plurality of redistributed circuit layers formed on the insulating layer, for electrically connecting the connecting pads of the first chip to the electrical contacts;

at least one second chip directly mounted on the redistributed circuit layers, the second chip being electrically connected to the redistributed circuit layers in one of a flip-chip manner and a wire-bonding manner; and

an encapsulant formed on the second chip, the insulating layer and the redistributed circuit layers, with the electrical contacts being exposed from the encapsulant.

2. The multi-chip stack structure of claim 1, further comprising a heat spreader attached to a surface of the encapsulant formed on the second chip.

3. The multi-chip stack structure of claim 1, wherein the second chip has an active surface and an opposed non-active surface, allowing the active surface of the second chip to be electrically connected to the redistributed circuit layers in the flip-chip manner, and allowing the non-active surface of the second chip to be exposed from the encapsulant.

4. The multi-chip stack structure of claim 3, further comprising a heat spreader attached to the non-active surface of the second chip.

5. The multi-chip stack structure of claim 1, wherein the second chip has an active surface and an opposed non-active surface, allowing the non-active surface of the second chip to be attached to the redistributed circuit layers, and allowing the active surface of the second chip to be electrically connected to the redistributed circuit layers via bonding wires.

6. The multi-chip stack structure of claim 1, wherein each of the electrical contacts is one of a bond pad and a metallic bump.

7. The multi-chip stack structure of claim 1, wherein the insulating layer is made of one of polyimide (PI) and benzocyclobutene (BCB).