Thin film transistor and manufacturing process thereof

• US 20070054441A1
• Filed: 09/08/2005
• Published: 03/08/2007
• Est. Priority Date: 09/08/2005
• Status: Active Grant

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Chunghwa Picture Tubes Limited
• Inventors: Hsu, Min-Ching, Mo, Yung-lung
• Granted Patent: US 7,508,036 B2
• Time in Patent Office: Days
• US Class Current: 438/149
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458

Abstract

A thin film transistor including a gate, a gate insulator layer, a channel layer, a source, a drain, and an ohmic contact layer is provided. The gate insulator layer covers the gate; the channel layer is disposed on the gate insulator layer above the gate; the source and the drain are disposed on the channel layer; the ohmic contact layer is disposed between the channel layer and the source and drain. The ohmic contact layer is constituted of a plurality of film layers. As mentioned above, the thin film transistor has an ohmic contact layer constituted by a plurality of film layers. When the thin film transistor is turned off, the current leakage thereof is lowered than that of conventional thin film transistor.

Claims

1. A thin film transistor, comprising:

a gate;

a gate insulator layer, covers the gate;

a channel layer, disposed on the gate insulator layer over the gate;

a source and a drain, disposed on the channel layer; and

an ohmic contact layer, disposed between the channel layer and the source and between the channel layer and the drain, wherein the ohmic contact layer is constituted by a plurality of film layers.

2. The thin film transistor of claim 1, wherein the ohmic contact layer is constituted by a plurality of N-doped amorphous silicon layers.

3. The thin film transistor of claim 1, wherein a material of the channel layer comprises amorphous silicon.

4. The thin film transistor of claim 1, wherein a material of the gate comprises metal.

5. The thin film transistor of claim 1, wherein a material of the source and the drain comprises metal.

6. The thin film transistor of claim 1, wherein a material of the gate insulator layer is selected from one of silicon oxide, silicon nitride and the combination thereof.

7. A manufacturing process of thin film transistor, comprising:

forming a gate on a substrate;

forming a gate insulator layer on the substrate to cover the gate;

forming a channel layer on the gate insulator layer over the gate;

forming an ohmic contact layer on the channel layer, wherein the ohmic contact layer is constituted by a plurality of film layers; and

forming a source and a drain on the ohmic contact layer, and the ohmic contact layer located between the source and the drain is removed.

8. The manufacturing process of thin film transistor of claim 7, wherein a method of forming the ohmic contact layer comprises:

utilizing a deposition process, wherein a deposition power is changed during the deposition process so as to form a plurality of film layers to constitute the ohmic contact layer having a plurality of film layers.

9. The manufacturing process of thin film transistor of claim 8, wherein a way to change the deposition power during the deposition process comprises turning off the power at a predetermined time interval during the deposition process.

10. The manufacturing process of thin film transistor of claim 7, wherein a method of forming the ohmic contact layer comprises:

utilizing a deposition process, wherein a deposition pressure condition is changed during the deposition process so as to form a plurality of film layers to constitute the ohmic contact layer having a plurality of film layers.

11. The manufacturing process of thin film transistor of claim 10, wherein a way to change the deposition pressure condition during the deposition process comprises changing the pressure at a predetermined time interval during the deposition process, so as to lower the deposition rate.

12. The manufacturing process of thin film transistor of claim 7, wherein the ohmic contact layer is constituted by a plurality of N-doped amorphous silicon layers.