Memory hub with internal cache and/or memory access prediction

• US 20070055817A1
• Filed: 11/01/2006
• Published: 03/08/2007
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Jeddeloh, Joseph
• Granted Patent: US 7,644,253 B2
• Time in Patent Office: Days
• US Class Current: 711/104
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address.

Claims

1. A memory hub, comprising:

a memory access device interface structured to interface with a memory access device;

a plurality of memory interfaces structured to interface with respective memory devices, each of the memory interfaces including a memory controller and a memory cache; and

a switch coupling the memory access device interface to each of the memory interfaces.

2-39. -39. (canceled)