Processor resource management

• US 20070055848A1
• Filed: 09/22/2006
• Published: 03/08/2007
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: Searete LLC (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Tegreene, Clarence, Myhrvold, Nathan, Wood, Lowell, Hillis, W.
• Granted Patent: US 8,181,004 B2
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

Embodiments include a device and a method. In an embodiment, a device provides a resource manager operable to select a resource management policy likely to provide a substantially optimum execution of an instruction group by comparing an execution of the instruction group pursuant to a first resource management policy applied to a hardware resource and an execution of the instruction group pursuant to a second resource management policy applied to the hardware resource.

Claims

1-46. -46. (canceled)

47. A device comprising:

a processor having a hardware resource associated with the processor; and

a resource manager operable to

compare an execution of an instruction group pursuant to an optimistic resource management policy applied to the hardware resource and an execution of the instruction group pursuant to a pessimistic resource management policy applied to the hardware resource;

select from the optimistic resource management policy and the pessimistic resource management policy a resource management policy likely to provide a substantially optimum execution of the instruction group; and

associate the selected resource management policy with the instruction group.

48. The device of claim 47, wherein the processor and the resource manager are formed on a single chip.

49. The device of claim 47, wherein the optimistic resource management policy assumes that the instruction group will execute in a substantially optimal manner.

50. The device of claim 49, wherein the optimistic resource management policy assumes that the instruction group will execute in a substantially optimal manner includes an optimistic resource management policy that assumes less than a preselected level of at least one error will occur during execution of the instruction group.

51. The device of claim 50, wherein the at least one error includes an occurrence of at least one of a hardware error, a fetch error, a memory error, a cache miss, a software error, an arithmetic overflow, a stale datum, a branch prediction error, an attempt to access forbidden memory, and/or an inability of an operating system to grant a request.

52. The device of claim 47, wherein the pessimistic resource management policy assumes that the instruction group will execute in a substantially sub-optimal manner.

53. The device of claim 52, wherein the pessimistic resource management policy assumes that the instruction group will execute in a substantially sub-optimal manner includes a pessimistic resource management policy that assumes greater than a preselected level of at least one error will occur during execution of the instruction group.

54. The device of claim 53, wherein the at least one error includes at least one of a hardware error, a fetch error, a memory error, a cache miss, a software error, an arithmetic overflow, a stale datum, a branch prediction error, an attempt to access forbidden memory, and/or an inability of an operating system to grant a request.

63. The device of claim 47, wherein the processor and the hardware resource are formed on a single chip.

64. The device of claim 47, wherein the processor is formed on a first chip and the hardware resource is formed on a second chip.

65. The device of claim 47, wherein the processor is formed on a chip and the hardware resource includes a device having a physical structure distinct from the chip.

55. A method comprising:

applying an optimistic cache management policy to a cache managed by a processor, executing an instruction group in the processor, and acquiring a context of the execution while the optimistic cache management policy is applied;

applying a pessimistic cache management policy to the cache, executing the instruction group in the processor, and acquiring a context of the execution while the pessimistic cache management policy is applied;

selecting from the optimistic cache management policy and the pessimistic cache management policy a cache management policy likely to provide a substantially optimum execution of the instruction group; and

associating a ghost page indicative of the selected cache management policy and of the context of the execution during application of the selected cache management policy with the instruction group.

66. The method of claim 55, wherein the applying an optimistic cache management policy to the cache includes

applying to the cache an optimistic cache management policy that assumes less than a preselected level of at least one error will occur during an execution of the instruction group.

67. The method of claim 55, wherein the applying a pessimistic cache management policy to the cache includes

applying to the cache a pessimistic cache management policy that assumes more than a preselected level of at least one error will occur during an execution of the instruction group.

68. The method of claim 55, wherein the selecting from the optimistic cache management policy and the pessimistic cache management policy a cache management policy likely to provide a substantially optimum execution of the instruction group includes

selecting from the optimistic cache management policy and the pessimistic cache management policy a cache management policy likely to provide a substantially optimum execution of the instruction group according to a preselected criterion.

69. The method of claim 55, wherein the selecting from the optimistic cache management policy and the pessimistic cache management policy a cache management policy likely to provide a substantially optimum execution of the instruction group includes

selecting from the optimistic cache management policy and the pessimistic cache management policy a cache management policy likely to provide a substantially optimum execution of the instruction group according to a preselected criterion, wherein the preselected criterion includes at least one of a successful completion of the instruction group, an unsuccessful completion of the instruction group, an uncertain completion of the instruction group, an exception, a time to execute the instruction group, a successful hit, an unsuccessful hit, a hit ratio, a correctly predicting a branch taken, an incorrectly predicting a branch taken, a correctly predicting a branch not taken, and/or an incorrectly predicting a branch not taken.

70. The method of claim 55, further comprising:

associating another ghost page indicative of the non-selected cache management policy and of the context of the execution during application of the non-selected cache management policy with the instruction group.

56-62. -62. (canceled)

71. A device comprising:

means for applying an optimistic cache management policy to a cache managed by a processor, executing an instruction group in the processor, and acquiring a context of the execution while the optimistic cache management policy is applied;

means for applying a pessimistic cache management policy to the cache, executing the instruction group in the processor, and acquiring a context of the execution while the pessimistic cache management policy is applied;

means for selecting from the optimistic cache management policy and the pessimistic cache management policy a cache management policy likely to provide a substantially optimum execution of the instruction group; and

means for associating a ghost page indicative of the selected cache management policy and of the context of the execution during application of the selected cache management policy with the instruction group.